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Implementation Of CCSDS Image Compression And AES Algorithm Based On FPGA

Posted on:2007-10-31Degree:MasterType:Thesis
Country:ChinaCandidate:R Q ChenFull Text:PDF
GTID:2178360212957485Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Along with the development of avigation, more demands are required on the effectivity, the real time property and the security of space image transmission. The space image data is in large quantities, and the channel bandwidth resources are limited, therefore the space image data compression algorithm has become hot recently. Besides, the high-speed hardware implementation is essential to fulfill the real-time transmission requirement.CCSDS (Consultative Committee for Space Data System) formally proposed the space image data compression algorithm standard in Nov. 2005. This recommendation has a low complexity and a simple structure to fit for hardware implementation. In this thesis, CCSDS image compression algorithm is implemented on FPGA, and Advanced Encryption Standard (AES) is also realized to encrypt the code stream for special applications.The main accomplished task of this thesis concludes the following parts:(1) The CCSDS codec is designed by studying CCSDS image compression algorithm deeply. Then the algorithm is compared with both JPEG2000 and SPIHT algorithms on complexity and performance.(2) CCSDS coder and AES algorithm are implemented on FPGA using Verilog HDL.(3) The complex modules are optimized, such as DWT. The performace of DWT is improved on both the clock frenquency and the used logic elements greatly by real-dualport RAM, which increases the data read and write speed, and by DSP block megfunctions, which process the kernel operations effectively.(4) The module pipelines are designed for the whole system to increase the data throughput, without additional chip area.(5) The whole system is functional and timing simulated in both Quartus II and ModelSim environments. The RS232 serial port is designed at the stage of FPGA verification to decrease the hardware verification time.The CCSDS image compression and AES encryption system are implemented successfully on Stratix EP1S25F780C5 pin of Altera. The system is verified on the effectivity and the encryption by a number of test images.
Keywords/Search Tags:CCSDS Image Compression, AES Algorithm, FPGA, Discrete Wavelet Transform, Bit Plane Coder
PDF Full Text Request
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