| Together with the development of space exploration technology, the demand for collecting data of space image is getting higher and higher. Due to the confliction between the limited communication bandwidth and the mass image data being downloaded, high speed image compression technology must be taken before onboard image data transmitted, which in turn calls for research on theory of image compression and leading compression algorithm. Therefore it is meaningful to research on the focus of VLSI hardware architecture for those compression algorithms, which are easily hardware implementation and are suitable for outer space environment.Published on Nov. 2005, CCSDS image compression algorithm is a leading algorithm oriented to space image. It is based on the Discrete Wavelet Transform (DWT). Due to it's well compression performance and high reliability, CCSDS image algorithm has extensive foreground in the field of space image compression. The main research of the thesis is on the focus of hardware architecture for onboard image compression, containing three part: (a) hardware architecture for 1D-DWT and 2D-DWT. (b) hardware architecture for Bit Pane Encoding(BPE). (c)the design of CCSDS algorithm using Handel-C language.In chapter 2, the main body of the CCSDS algorithm is introduced; Its performance and hardware complexity is analyzed by comparing CCSDS with JPEG2000 and SPIHT. It is concluded that CCSDS is suitable for deep space exploration and earth-approaching observation.Hardware architecture for 1D-DWT and 2D-DWT are discussed in chapter 3. Due to the longest path in the direct mapped lifting architecture of 9/7M DWT, it is impossible to get higher running frequency. According to the pipeline design rule, a new method based on 4-leveled pipeline is designed, which minimizes the longest path and significantly improves the timing performance. Based on 1D-DWT, a 3-leveled 2D-DWT is designed, in each level row-DWT and column-DWT is processed by parallel and pipeline methods. .In the BPE part of chapter 3, during preprocess stage, it minimizes the wavelet coefficient memory access time by using coefficient depth instead of coefficient itself, the coefficient depth will be used for computing coefficient type. In the stage of Bit Plane Scanning, 16 coefficient blocks are scanned at one time, which accelerates the subsequent AC entropy process. An optimized memory structure is proposed to speedup AC entropy process. In the Byte Builder module design, a valid architecture is presented to linkup the variable length codeword without any redundancy.In chapter 4 the Handel-C design process is discussed. After comparing the traditional C language with Handel-C language, the"sequent mechanism"is analyzed, then introduced some rules on rewriting C code to Handel-C code. Finally, a method is proposed to resolve the problem of connecting different clock domain modules.The main achievements of the thesis can be summarized as follows.:1. An optimized lifting scheme of 9/7M DWT based on 4-leveled pipeline was presented. Due to the longest path in the direct mapped lifting architecture of 9/7M DWT, it is impossible to get higher running frequency. According to the pipeline rule of inserting pipeline register in the forward cutting set, a new method base on 4-leveled pipeline is presented, which minimizes the longest path and significantly improves the timing performance.2. Two improvements on the memory structure of BPE scanning information were proposed. During the stage 4, the wavelet coefficient scanned bits can be de-seriated before save to memory location; The mapped symbol of the scanning word is saved to the memory instead of the scanning word itself, Because the mapped symbol has not"null"symbol, the AC Entropy Encoder would not access to invalid memory location. As a result the speed of AC Entropy can be enhanced.3. A valid architecture was presented to linkup the variable length codeword without any redundancy. 1-8 bits can be compactly jointed together during one clock.
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