FPGA Design And Implementation Of High Speed Discrete Wavelet Transform In Space Image Compression System

With the rapid development of space imaging technology,the resolution and data rate of satellite images are getting higher and higher.The amount of data is gradually increased,and requires a lot of storage capacity and transmission bandwidth.Therefore,the research on the effective space image compression system is very meaningful in reduction of the requirements of memory capacity and transmission bandwidth.In the current space image compression system,the compression performances of the frequently used algorithms such as DPCM and DCT are not sufficient,and the DSPbased implementation fashion has low processing speed and high power consumption,whereas FPGA tends to provide high computing performance with low power consumption,however,it remains a challenging problem to implement complex compression algorithms in FPGA.In order to solve these problems,in this thesis,the CCSDS 122.0-B-1 space image compression standard is studied,and the hardware architecture in FPGA for multi-level two-dimensional wavelet transform is proposed.The main works of this thesis are listed as follows:1.The multi-level two-dimensional wavelet transform in CCSDS 122.0-B-1 space image compression standard is analyzed in detail,and the hardware feasibility and some parameters of this standard are evaluated and compared with the related algorithms in the other image compression standards.2.The characteristics of two-dimensional wavelet transform are analyzed,and the hardware architectures of multi-level two-dimensional 9/7 wavelet transform and 5/3 wavelet transform are designed,which have high processing rate,less external resources,and can meet the real-time processing requirements.3.According to the mission requirements of space image compression system,the hardware scheme and reasonable circuit designing are putted forward.4.The multi-level two-dimensional wavelet transform scheme is realized by Verilog HDL language.Its correctness and performance are verified.The performance of 9/7 wavelet and 5/3 wavelet are evaluated and compared with the frequently used decorrelation methods.The experimental results demonstrate that,compared with the traditional structure repetitively using filter for multi-stage wavelet transform,the proposed architecture can meet the requirement of real-time image processing,reduce the use of off-chip RAM,and provide favorable conditions to the subsequent data encoding and transmission.