Research On Bit-plane Encoding Of CCSDS Image Compression And Implementation On FPGA

With the development of space exploration, space image data increase rapidly, which causes great pressure on the onboard memories and communication channels. To solve this problem, real-time image compression is an effective technique. In 2005 CCSDS proposed standard for image compression algorithms. It supports lossy and lossless compression and needs less resource due to low complexity, which is important to space data compression.After the study of the CCSDS image compression standard, this paper presents bit-plane encoding of the CCSDS image compression algorithm based on FPGA. The major work is listed as follows.(1) The research on CCSDS image compression standard is carried out, focusing on the design and analysis of the bit-plane encoder's structure.(2) The CCSDS bit-plane encoder is implemented with Verilog Hardware Description Language. The bit-plane encoder consists of DC encoder, AC block depth encoder and AC encoder. To improve coding speed, the Ping-Pang operation and pipeline method are utilized.(3) The functional simulation and timing simulation of each module and the whole encoder are implemented in the modelsim simulation environment. And then the simulations are proved to be practically correct in the Altera FPGA platform. Experimental results show that the encoder has low complexity and high coding efficiency.(4) Based on the analysis of the designed encoder, the optimization is performed on the time or resource consuming modules.