Based On The Ccsds Image Compression Algorithms (9,7) Wavelet Algorithm Architecture And Fpga Implementation

With the rapid development of aviation technology and the increasing number of satellite payload, more and more space image acquisition has become the growing demand, so data of transmission has become very great. The large volume of image data will greatly increase the pressure of memory storage, communications channel bandwidth, and the computer's processing speed. Since the spacecraft memory capacity is limited, and the channel bandwidth is extremely rare circumstances, image data compression become an inevitable solution.In November 2005, CCSDS (The Consultative Committee for Space Data Systems) released of the latest image data compression standard. With its low bit-rate transmission of data compression, it has broad application prospects in the space field. Algorithm uses wavelet transform and bit plane coding theory and supports image compression of two ways-lossless compression and loss compression, two scanning ways -frame image and pushing image. It also supports the controllability of transmission rate and image quality. The needs of image compression is met in the near - Deep space exploration mission.In this thesis, the (9,7) Integer Wavelet hardware architecture is major researched. The C and Verilog code are written to verify the algorithm and structure. And the BIT file is successfully downloaded to the self-developed experimental FPGA development board. Also the algorithm is successfully verified.This thesis has the following aspects.1) Based on the CCSDS image compression algorithm recommendations, the algorithm is deeply researched. And based on this we designed the VLSI hardware architecture of the algorithm.2) Based on the CCSDS image compression algorithm recommendations, the (9,7) wavelet integral structure of FPGA implementation is designed. Parallel process pipeline design is achieved and it improves the utilization of hardware resources and the speed of transformation. In the end the architecture is certified on the FPGA board which is the main innovative achievement of this thesis.3) Based on the algorithm and hardware architecture, the FPGA circuit schematics is designed and an experimental board is developed. The accuracy of algorithm structure and feasibility is successfully tested and verified through communications between the serial port and computer.