The Research On Low Power Built-in Self-test Design

Deep-sub-micron process technology and design methodology of SoC based on IP (Intellectual Property) reuse bring the great challenges to the design and testing of the integrated circuits. To reduce the test complexity and cost, Built-in Self-test (BIST) technique is widely used in chip design. In general, circuits consume more power in test mode than in normal operation, and the widely usage of BIST makes the problem more serious.After analyzing the BIST structure and power model, the paper makes research on the algorithm and realization of lower power BIST aiming at two kinds of BIST architecture: the test-per-clock and test-per-scan. In order to meet chip testing power limitation, the design methods for low power BIST circuit and reasonable test strategy are studied.For the test-per-clock BIST, the research to reduce testing power mainly focus on optimization of test pattern generator (TPG). Experiments demonstrate the seed of linear feedback shift register (LFSR) will influence the testing power greatly, and the existence of some useless test patterns also reveals some association with the low power design. By the simulated annealing algorithm for global optimization, the algorithm of dividing the testing pattern into groupings is deduced and verified. Based on the algorithm, some low power BIST techniques are put forward, such as controllable LFSR, jumping logic for low power TPG etc.. The experiments show that these methods can reduce testing power efficiently. Aiming at some heavy inputs which influence the testing power greatly, a new simple BIST structure for low power testing is presented and verified. Some discussions based upon the theory of probability are also made to reduce the transitions introduced by these heavy inputs.For the power consumption problem of test-per-scan BIST, some basic low power methods are discussed such as adding MUX circuits, modifying the scan units. A modified clock scheme is also discussed, which can lower the transitions in the circuit under test (CUT), as well as in the scan path and the clock tree. After modeling by the relation between the observability of sequential logic and the fault coverage of CUT, an algorithm is deduced to solve the excessive peak power problem by partitioning CUT's data transfer graph.A low peak power Built-in self-test (BIST) scheduling algorithm for system-on-a-chip (SoC) is presented and a compact power model of scan based BIST is proposed. Based on the model, excessive peak power during testing can be avoided by adjusting the BIST period and controlling each BIST's startup.At the end of the paper, a summary is given and also some problems are discussed.