Optimizing Methods In The Design Of Built-in Self-Test For Digital Circuits

Built-in Self-test (BIST) performances the test through an embedded test architecture in a circuit under test (CUT). As an at-speed test in the Design for Testability (DFT) of digital system, BIST has become a necessary part of circuits such as VLSI, Multi-Chip Module (MCM), Intellectual Property (IP) cores of System on a Chip (SoC) due to its efficiency and maintainability. This dissertation studies on the optimizing methods of Logic BIST (LBIST) and Memory BIST (MBIST).In the optimization of MBIST design, a new programmable SRAM BIST controller and the related encode format of instruction are proposed. Then an automatic generation system of SRAM BIST IP core is designed, which can generate BIST IP core according to the type of SRAM and March test selected by the user. The experimental results show that the automatic IP core generation system can work correctly, possessing the abilities to support various tests, e.g. synchronous/asynchronous SRAM test, known March test, optional March test, Data Retention Faults (DRFs) test, at-speed test and capture of fault address and data etc..While in the optimization of LBIST design, combining the weighted pseudorandom pattern generation with the vector-inserted low-power BIST design, this dissertation proposes a test pattern generation based on LFSR (linear feedback shift register)–CA (cellular automata) and genetic algorithm (GA) , not only reducing the length of test pattern, but also reducing the power consumption. The experimental results based on ISCAS'85 benchmark circuits prove that advantages: the total and average power down to 73%-95%, and the peak power down to 26%-60%. It means the power consumption has been reduced obviously, and the length of test pattern is reduced also effectively, without losing the fault coverage.The main original contributions of this dissertation are as follows: first, proposing a programmable implement of known and user-defined March tests by the uses of whole-element-encoded formats in MBIST controller; secondly, cooperating the reducing of test length with the reducing of power consumption, that is, designing a low-power BIST based on weighted TPG (test pattern generator) (LFSR-CA) and genetic algorithm; and thirdly, developing a hardware demonstration instrument for the optimizing design of BIST under the controlling of the boundary scan test controller.Experiments indicate that the optimizations of BIST design in this dissertation are efficient.