Research On Low Cost Deterministic Built-in Self Test (BIST)

Along with advancement of integrated circuit processes and enlargement of chip scales, design of chip enters the era of system on a chip(SoC). In those large SoC designs, integration of various intellectual properties (IPs) makes enlargement of test data and test control of IPs difficultly, which results in that the traditional test method utilizing Automatic Test Equipment(ATE) does not meet requirements of test SoC. Built-in self-test (BIST) utilizes little logic circuit integrated in circuit under test(CUT) to test CUT, which is widely known as a effective design-for-testability(DFT) for SoC design, and becomes a new research hotspot in the test techniques.The design aim of BIST is that test with high fault coverage is implemented by little hardware overhead in short time. That is, BIST requires little hardware overhead, short test time, high fault coverage. In addition, correlation between consecutive test patterns is very low, so power under test mode is higher than that under normal mode, which makes test power exceed threshold of power easily, in turn burns CUT. Therefore, reduction of test power is also other design aim of BIST.This paper focuses on test cost of deterministic BIST, including test hardware overhead, test time and test power, and makes some researches by optimizing deterministic BIST. The main contents of this paper include:(1) Research on the properties of Twisted Ring Counter(TRC). Based on the sequence generated by TRC, the redundant property, transition counts property, and the equivalent property of TRC have been studied. These properties of TRC obtained by us can be utilized to guide design of deterministic BIST based on TRC.(2) Aiming at a little test data of deterministic BIST, the vertical compression deterministic BIST based on TRC is studied. Firstly, a seed selection algorithm suiting the deterministic BIST scheme using counter as test pattern generator is proposed, in which test cubes in deterministic test set is utilized to determine seeds. Therefore, few seeds can be stored instead of the deterministic test set when BIST architecture is designed. Secondly, because there are many unuseful patterns in sequence generated by each seed, a removing redundant sequence algorithm is proposed to inhibit generation of the redundant sequence, which utilizes the position difference of the last non-redundant segments generated by the previous and the next seeds to determine whether the redundant segments of the next seed can be inhibited. Lastly, because the flip-flops of CUT are configured into test pattern generator, which makes the flip-flops lose capturing responses, so a low hardware overhead response compactor is proposed to compact the responses from the primary outputs and pseudo-primary outputs. The proposed compactor is composed of one MISR and one improved elementary tree space compactor consisting of AND, OR, and XOR. Because XOR is introduced into the traditional elementary tree space compactor, compaction efficiency and hardware overhead can be optimized.(3) Aiming at a little test data and short test time of deterministic BIST, the two-dimensional compression deterministic BIST based on TRC is studied. Based on the proposed vertical compression algorithm of TRC and removing redundant sequence algorithm, Two two-dimensional deterministic BIST schemes are proposed to reduce test data and test time. In the first scheme, horizontal compression of input reduction and vertical compression of twisted ring counter are combined. The vertical compression based on twisted ring counter is utilized to reduce the number of test patterns, and the horizontal compression based on input reduction is utilized to reduce the number of bits per test pattern so that the length and the width of the test set can be reduced. In conclusion, because the length of TRC seeds is reduced by input reduction, so test data and test time can be significantly reduced, but order of inputs must be adjusted. In the second scheme, horizontal compression of LFSR encoding and vertical compression of twisted ring counter are combined. Here one LFSR seed is firstly decoded into one TRC seed, and the TRC seed then generates test patterns to detect faults. Theoretical analysis shows that the length of LFSR of the design is reduced up to smax+2 from smax+20, which increases the encoding efficiency. When BIST architecture is designed, LFSR seeds can be stored instead of TRC seeds. Therefore, test data can be reduced. In addition, each TRC seed only generates few test patterns, so test time can reduced.(4) Aiming at a little test data, short test time and low test power of deterministic BIST, the deterministic BIST based on reconfigurable TRC and the deterministic BIST based on scan slice partition scheme are studied. In the aspect of the deterministic BIST based on reconfigurable TRC, based on the proposed vertical compression algorithm of TRC, Two reconfigurable deterministic BIST schemes are proposed to reduce test power by freezing a selected part of inputs. In the first scheme, reordering inputs is executed to place the inputs meeting the freezing conditions in the side close to the scan out port, and all inputs after reordering inputs are grouped so that partial reseeding and partial freezing of groups are achieved. In this way, test power and test data can be reduced. In the second scheme, the architecture of traditional scan cell is modified to make the scan cell have not only scan function but also bypass function so that the half of all inputs are activated, and the other half are frozen. In this way, test power can be reduced. In addition, the proposed'odd-full-and-even-half'reseeding is adopted, so the seeds with even sequence numbers only require half test data. In this way, test data can be also reduced. In the aspect of the deterministic BIST based on scan slice partition scheme, an optimization scheme based on deterministic BIST of scan slice partition is proposed to further reduce test data and test power. Firstly, Input reduction is introduced to identify some compatible sets of inputs, and choose one scan cell from each compatible set to form a scan chain so that the length of scan chain is reduced, which in turn reduces the number of control bits and test time. Secondly, a random reordering inputs algorithm is proposed to order the scan chain after input reduction so that test data and test power are reduced. Lastly, a test pattern partition algorithm which always leads to the better results is proposed. Combining the three proposed optimization algorithms, test data, test time and test power can be significantly reduced.