Study On Design For Test Of Digital Signal Processor Chip

In recent years,with the continuous development of integrated circuit,chip scale is more and more large,the complexity is higher and higher.The increase of chip integration brings many challenges to design and testing,among which testing has become an urgent problem to be solved.The testability design of a home-made DSP(Digital Signal Processor)chip is studied in this paper.The main work is as follows:(1)In order to Test the I/O port of the chip,JTAG(Joint Test Action Group)module is designed based on IEEE1149.1 protocol.In order to enable JTAG to control testability design logic on a chip and to debug the Central Processing Unit,the instruction set of JTAG was extended.While retaining four IEEE 1149.1 mandatory instructions,six CPU debugging instructions were added,which enabled CPU designers to debug CPUs through JTAG.Two built-in memory test instructions were added to enable JTAG to control the start and stop of built-in memory test.(2)In order to test Memory,SRAM(Static Random Access Memory)is designed with built-in self-test structure.By analyzing some static and dynamic faults that can't be detected by March C+algorithm,March CP algorithm is proposed.The complexity of this algorithm is 23N.The total complexity of March C+algorithm and March CP algorithm is 37N,and the total complexity is within the acceptable range.March C+algorithm and March CP algorithm were combined to test the SRAM memory,and the test coverage of 48 static faults was 95.83%,and the test coverage of 52 dynamic faults was 73.08%.(3)In order to compress the scan chain test data,a cyclic shift reference section compression method was proposed to overcome the shortcomings of a mirror reference section method.The cyclic shift reference section compression method,on the one hand,makes up for the deficiency of the mirror reference section when the original reference section is symmetric about itself,and on the other hand,increases the original two groups of reference sections to four groups,which increases the compatibility probability of the scan section and the reference section.By calculating the Hamming distance between the four groups of reference sections,the rationality and effectiveness of the cyclic shift reference sections were demonstrated.The results show that the cyclic shift reference slice compression method can compress the test vectors of six kinds of circuits,and the average compression rate reaches 69.33%.(4)The logic synthesis of testability design related modules was carried out,and the chip function modules were inserted with scanning chain and generated with automatic test vector,etc.Finally,the back-end designers used Huahong HHGRACE F018Q6D0 process to carry out back-end design and layout realization.