Ic Low-power Built-in Self-test Technology

With the development of integrated circuit technology, bring the increase in the integration and the complexity of chip can add difficulties and the cost of the test, thus bringing a big challenge to the integrated circuit testing. In the meantime, it also makes a more urgent demand to the development of testing theory and testing technology of integrated circuit. Built-in-self-test integrating the test circuitry into the chip, and supporting the chip's at-speed testing, has been an important strategy to solve the testing difficulty of chip and reduce the testing cost. However, because of very low relativity among random testing vectors produced by testing vector generator used in built-in-self-test, power consumption under testing mode may be much greater than that in normal operation. Higher testing consumption can reduce the reliability and yield of chip, increase the package cost, shorten the standby time. So the problem of low power consumption during test is a new challenge to the wide application of BIST.In order to solve the power consumption problem, especially high power consumption problem resulted from the deep sub-micro technology and system chip (SoC), this paper presents a design scheme for test vector generator on the basis of random single input change testing theory. The principle is to add logic switching circuit on the basis of linear feedback shift register to change random testing vector output by LFSR, thereby rearranging the sequence as random single input change one. The new sequence can reduce switching activity of under-test circuit to realize low power consumption during testing.Theoretical analysis and the result of power consumption simulation indicate the power consumption from random single input change is lower than that produced by traditional random test vector. The research work provides an improvement on the testing theory of single input change.The paper introduces a circuit realization method of built-in-self-test theory under FPGA Advantage environment. By VHDL describes test pattern generation, test response analyzer, built-in self-test controller and under-test core. The simulation is carried out under FPGA Advantage integrated environment and realized with FPGA (EP1C6Q240C8). Theoretical analysis, simulation result and hardware verification on the basis of KH-310 confirm that schematic circuit realization method of built-in self-test is correct and effective. This method can be applied to BIST in the core of ASIC, IC or IP for shortening testing time and reducing testing cost. The paper proposes a "flexible signal processing circuit", in which, charge coupled devices is the core of a FIR (Finite Impulse Response) filter. This circuit can be used to post-adjust the frequency parameters of a testing system (e.g. Instrument, sensor), extending the frequency band and reduce testing distortion. The main advantage of the design is its "flexibility". If The technology can be used to many kinds of measuring system by changing the clock frequency when CCD is working, and has a great value for engineering application. When FIR filter is realized with very large-scale integrated circuit, the test of the filter becomes more and more difficult because of high integration and optimized design, especially when people upgrade the performance requirement of the FIR filter, the orders of the filter is added continuously, the inherent depth on FIR structure further reduces its testability. A way to solve this problem is to design testability into the filter and find an effective BIST testing scheme at the same time. The paper presents a bidirectional testability design according to charge transfer property of CCD. Through re-use the delay unit in circuit, pipepline delay unit is changed to scanning chain to transmit testing sequence, thus reducing test difficulties of FIR filter and improving testability.