A Study On Memory Built-in Self-Test And Functional Core Testing

With the progress in IC manufacturing process and innovation in methodology based on IP (Intellectual Property) reuse, SoC (System-on-a-Chip) is widely used in consumer electronics. At the same time, the complexity of SoC architecture increases dramatically, this factor has had a profound impact in how SoC can be tested effectively.It has become a trend that a variety of embedded memories are integrated on SoCs. Due to the limit of the ATE storage capacity, it is impossible to apply test vectors from ATE directly. In order to compress test vectors, a new MBIST architecture is proposed in this paper. All the vectors needed are generated by the MBIST circuit, and the embedded memories are tested automatically. This architecture supports various kinds of memories, such as single-port, dual-port SRAM, Cache memory, CAM, etc. A new algorithm for CAM test is also used to release the difficulty in testing CAM.A JTAG port is a standard test interface, it uses boundary-scan technology, which enables engineers to perform extensive debugging and diagnostics on a system through a small number of dedicated test pins. In this paper, JTAG interface is used to test ARM core. By making use of the ability of extending scan chains, it is also used to initialize MBIST and scan out the final result.In general, in the process of testing SoC, especially for some macro cells, the efficiency is fairly low. A test scheduling and vector-merge method is proposed to solve the problem. It shows that the number of test patterns and time required to test the CPU core is reduced by 50% or so.