The Design And Realization Of The Built-in Self Test In X Microprocessor

X processor is a very much complex microprocessor, which contains Caches, microcode ROM, instruction prefetch unit, dynamic branch prediction unit, instruction decode unit, integer unit, multi media extension unit, floating point unit, segment and page management unit, bus unit, dual processor unit and APIC. For such a complex microprocessor, only relying on extern test to achieve desired fault coverage will be very impractical, thus, we must embed the built-in self logic in it to improve the processor's testability.In this paper, based on the study of all kinds of BIST technologies and ways prevailing currently in the world, a scheme of the design of BIST oriented to the X microprocessor's features and specified test requirements is proposed. This scheme considers the internal structure of X microprocessor fully, as well as the processor's processing ability, address-data bus architecture and its debugging and testing logic. So this BIST design can provide very high test coverage and fault coverage at a very low hardware cost and meets the X processor's testing demand very well. And this BIST design has been realized on the X processor which has been tapped out and functions correctly.The X processor's built-in self test is partitioned into two stages: structural BIST and microcode BIST. During structural BIST, the X processor's instruction flow path, microcode ROMs and some other important circuits are tested; during microcode BIST, the X processor's instruction unit, all function components and large memory arrays are tested by the microcode programs which have been stored in the microcode ROMs in advance, and processor's control path and data path are also tested at the same time. About 70 percent of the processor's logic is covered during BIST; by organizing the BIST process carefully and utilizing the processor's scan structure effectively, we provide a very convenient BIST use and diagnosis interface.