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On test generation and fault diagnosis in scan built-in self-test

Posted on:2007-11-03Degree:Ph.DType:Thesis
University:The University of IowaCandidate:Yu, ChaowenFull Text:PDF
GTID:2458390005984899Subject:Engineering
Abstract/Summary:
This thesis discusses some solutions to the problems about test cost, test quality, and fault diagnosis in scan BIST.; First, a new method to design Markov sources is proposed to reduce test cost. The design attempts to match probabilities of 1 to 0 and 0 to 1 transitions in consecutive bits of a set of test vectors, taking into account that the transition probabilities may be different for different bit positions. Experimental results show that the proposed method considerably reduces the hardware overhead and test lengths required for 100% fault coverage.; Second, a hardware efficient weighted pseudo-random scan BIST test pattern generator for n-detection of single stuck-at faults is proposed for improving defect coverage. In the proposed pattern generator some scan chains are grouped together during weighted random testing. Each group of scan chains is driven by a single weighted pseudo-random source. Experimental results show that both the test length and the hardware overhead increase slowly with n for n-detection of single stuck-at faults. The test length growth rate is much lower than n.logn expected for pseudo-random tests. The rate of growth of hardware overhead with n is also modest.; Third, a circuit independent weighted pseudo random BIST pattern generator based on bit-flipping is investigated. In the proposed pattern generator, all the circuit dependent information is stored in memories so that different circuits can use the same BIST structure by only changing the data in the memories. New approaches are proposed for compressing and storing the bit-flipping data. Experimental results show that the proposed method reduces the size of the memory considerably while using similar test lengths as a recent method based on bit-fixing.; Finally, a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment is proposed for BIST fault diagnosis. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously proposed random partitioning scheme is used to generate additional partitions. Experimental results show that the proposed method always achieves better diagnostic resolutions than the methods using random partitioning scheme and using interval-based partitioning scheme.
Keywords/Search Tags:Test, Fault diagnosis, Scan, Partitioning scheme, Proposed, BIST, Experimental results show, Pattern generator
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