The Behavioral Modeling Of Foldig And Interpolating ADC Based On Simulink

High-speed analog to digital converters (ADC) is the most important part of thesignal processing system, and is widely applied in measuring instruments, digitaloscilloscope, digital communications， radar and other fields, so the research of ADC iscritical. Among so many ADC structures, folding and interpolating ADC has manyadvantages, such as high-speed, low-power-consumption, small-size and be easycompatible with digital process etc. This thesis focuses on the analysis of maincomposition module in the folding and interpolating ADC and it’s behavioral model.The main research content include the clock jitter and the offset voltage of opamp insample-and-hold circuit, the nonlinear gain in pre-amplifier and folding circuit, therestrictions on bandwidth in folding circuit, the resistance mismatch in interpolationcircuit and the offset voltage in folding operational amplifier and comparator.With the simulation of the behavioral modeling established by simulink, the resultsshow that in order to complicate a10bit folding and interpolating ADC with SFDR is65.17dB, SNR is62.96dB, INL is0.4LSB, DNL is0.37LSB, the designer should ensurethe performance indices listed below. The input offset voltage of op-amp is less than0.8LSB, the clock jitter is within27ps, the gain of pre-amplifier and folding circuit arerequired to be5dB and7dB, the bandwidth of folding circuit is25times than themaximum bandwidth of the input signal, the offset voltage of the comparator is lessthan0.3LSB. According to the simulation results, the performance indices can be usedto guide the design of ADC circuit.