Study On VLSI Design Of Low Power Embedded Microprocessor

With the development of 1C fabrication techniques, the speed and integrity of the chip increase greatly, which makes the power density increase dramatically. In order to prolong the battery life of the portable device and decrease the cost of package, the power consumption should be considered in chip design. Embedded microprocessor is the core of System-on-Chip, and it is the most advanced in digital 1C design. So the design of low power embedded microprocessor is one of the most important research areas.Based on the analysis of the 1C power consumption, the dissertation studies the usual low power design techniques and gives the low power design flow in this work. By comparison of usual instruction sets, we select an optimal instruction set and design a 32-bit embedded microprocessor. Based on this processor, we study the low power techniques for embedded microprocessor. At last the verification of the processor and the implementation result are given.The work in this dissertation can be concluded as following:1. A 32-bit embedded microprocessor named as SRISC is designed with a top-down methodology. The instruction set of this processor is compatible with MIPS32-4Kec, and the processor has passed the FPGA verification and been taped out.2. For we can decrease the power consumption more at higher design level, the dissertation studies the system-level low power techniques, dynamic power management (DPM). A phase-lock-loop is embedded in SRISC and one PLL control register is designed, so SRISC can vary the clock frequency dynamically. A power manager is designed in SRISC, which can mange the power modes and make the SRISC energy-efficient.3. At architecture-level, the dissertation focuses on the low power design of calculation unit, control unit and memory modules. The calculation unit involves the adder, the multiplier and the divider. The control unit and memory modules include operand isolation, instruction decoder, Cache, etc. On the analysis of the usual architecture of these units and the latest techniques for these units, we optimize these modules or propose some modified solutions.4. The function verification of microprocessor is very important. The verification strategy for SRISC is in two steps. One step is the verification based on reference model, which includes the reference model of SRISC and the test vector generator based on testcase, and this step verifies the processor core more. The other step is the verification based on applications, which can be benchmark program, OS, etc., and this step focuses on the verification of the memory interface.5. A demo system with the name, uCRISC, is designed based on SRISC. The system consists of SRISC processor, Wishbone bus, memory controller, and otherperipherals. The system is implemented on FPGA, which can verify the SRISC processor and test the SRISC chip. An embedded OS, uC/OS-II, is ported to uCRISC, which simplifies the advanced development of SRISC. The innovation of this dissertation can be described as following:1. A modified DPM is used in SRISC. With high-performance PLL, SRISC can work with more clock frequency, which guarantees the energy-efficient. The power mode is switched by hand shaking, which makes the mode switch more effective and the control easier.2. A multiplier with the operand exchange and transformation is proposed. According to the relativity of the operands, the operands are exchanged and transformed to eliminate the switch of the operands, which can lower the power consumption of the multiplier.3. On analysis of the usual architecture of the divider, a dual-bit divider is proposed, which can improve the execution efficiency greatly. With the same calculation ability, the proposed divider consumes less power.4. A power evaluation method for operand isolation is proposed. The proposed method can guide the utilization of operand isolation in chip design.5. According to the characteristic of SRISC, a serial access of tag and data RAM and the tag-...