Design Of Low Power Voltage Controlled Oscillator For Iot Applications

The brisk pace of Io T technology is now reshaping our urban lifestyle in a profound way.Among this great revolution,short-range wireless communication working at ISM band such as Wi Fi,Bluetooth and Zigbee plays a vital role in terminal application.Thus,the demand of low voltage,low power and high quality radio frequency(RF)transceivers blossoms rapidly,which stimulates the development of phase locked loops(PLL)and frequency synthesizers.As a key part of PLL,voltage-controlled oscillator(VCO)has long been the research focus since it provides reliable local references and has significant impact on the performance of the whole communication system.Thus,the study of low power,low phase noise VCO shows magnificent research value and engineering application benefits.In this thesis,a low power VCO working at ISM band RF transceivers is proposed for Io T applications.In order to alleviate the effect of frequency pulling from integrated PA on chip,the VCO core is chosen to work at 4.8?5.0GHz,and cascaded by quadrature divider-by-2 circuit which buffers the output as local oscillator.Based on the thorough understanding of conventional VCOs and the insights of the phase noise behavior,this paper develops further innovation of Class-C VCO and presents a novel dual-loop-feedback structure.The new structure compares the bottom value of the VCO output voltage with the overdrive voltage of the current source and creates feedback to self-adjust the coupling voltage of the cross coupled pairs which realizes the dynamic DC bias.Comparing to the traditional structure,the improved scheme further promotes the conduction efficiency of the transistor as well as power dissipation,lowering phase noise and shows better PVT robustness.To avoid squegging,detailed analysis of large signal circuit stability is adopted under appropriate approximations and the conclusion has been verified by simulation to ensure the reliability of the circuit.Also,based on the traditional current mode logic(CML)circuits,a modification of traditional highspeed frequency divider-by-2 circuit is improved in this paper.The new circuit adds few transistors in the conventional structure to mitigate the problem of mismatch between rise and fall time.Furthermore,it can decrease the power consumption and enhance the output swing.Additionally,an automatic frequency calibration circuit based on dichotomy is fulfilled and verified under certain platforms.The prototype of the VCO is designed on the TSMC 40 nm CMOS technology and verified by postlayout simulation.The simulation result shows that under 0.8V supply voltage,the VCO can provide quadrature output at 2.4?2.5GHz properly whose phase noise less than-121 d Bc@1MHz and roughly consumes 1m W.A PLL and transceiver chip applying this circuit scheme has been taped out and tested preliminary whose results show that the circuit can work properly.The out-of-band phase noise of the overall PLL is-116 d Bc@1MHz which can satisfy the demand of Io T communication applications.