The Research Of Low Power Scheme In LCD Controller

When designing the LCD Controller, power consumption is a critical issue because low power LCD Controller could avoid changing batteries frequently, and alleviate the problems of float of parameters, reduction of reliability, and decrease the cost of package caused by high power consumption.In this dissertation, a low power LCD Controller is presented, which could be applied for color / monochrome LCD with embedded 320KB Display Cache. This LCD Controller supports different kinds of CPU and operation system; it provides flexible features, such as dummy display, ink layer, hardware cursor, hardware rotation, picture in picture and 2D image operations; and its 32bit internal data bus provides efficient bandwidth to accelerate the display refresh of images.In order to implement low power design, a series of strategies have been adopted. At the system level, system clocks allocation method, dynamic power management, bus isolation and distributed storage structure are employed. These methods reduce the power consumption of the system by decreasing the operation frequency, forbidding invalid operation and alleviating the bus load. At the algorithm level, the Adaptive Run Length Encoding is employed, which cut down the power consumption by compressing the data in Display Cache and thus reduce the access frequency. At the RTL level, the clock gating logic and operand isolation logic are inserted by Design Compiler to further reduce the power consumption.The LCD Controller is described with VerilogHDL. After functional simulation and FPGA verification we analyzed the power consumption of the design. The average power at the top level is only 11.17μW. The module consuming most power is 320KB Display Cache, followed with Graphic Processing module and Clock Generator. The experimental results show that the architecture and low power strategies of the high performance, high integration LCD Controller is feasible.