Study And Implementation Of Random Test Program Generator For Microprocessor Verification

Microprocessor verification is a necessary phrase during microprocessors design. How to automatically generate comprehensive test programs is always the focus of the verification task. Random test program generator (RTPG) is such a kind of important tools to achieve these aims which are used in the test phase of the microprocessor design and implementation. According to some principles it randomly generates sequences of instructions. Thus RTPG can construct interesting cases that are hard to be produced by other methods. Also, it brings out good testing intensity and high rate of coverage. This paper presents a system for automatic simulation and verification of pipelined microprocessors. In this system, multiple FSMs (finite-state-machine) are used to simulate the behavior of the whole processor. As a result, this method has made the system simple and efficient. When a new function unit is added to the microprocessor, the only thing we need to do is to add the FSM corresponding to the function unit to the system. Another feature about our system is that it deals well with the branch instructions. Test programs generated by our RTPG have the features of no infinite loop, not entering illegal states, controllable data dependency, flexible program size, and data cache testable. Also, for each instruction we have developed a coverage array which will guide the generation of the instruction. The RTPG Experimental evaluation of the generated test programs indicates that our RTPG, with the guidance of the coverage tool, only needs to generate a small number of test programs to sustain high coverage. Some test results are given at the end of this paper. The system had got an encouraging result in the simulation and verification of the microprocessor developed by Tsinghua University.