Research On Ultra-low-power Microprocessor Based On Instruction Type To Dynamically Turn Off Circuit Module

With the continuous development of integrated circuit technology,the size of the process continues to shrink,and the chip scale and operating frequency have been greatly improved.The chip speed and area are no longer the main factors and design goals of chip designers.At the same time,with the rise of applications such as Internet-of-Tings,wearable electronics,and implantable mecdical electronics,low-throughput,power,and energy-sensitive chip designs have begun to receive widespread attention,and almost all of these chips are always powered by battery.Power consumption has replaced speed as the designer's primary consideration.This paper mainly focuses on the problem that the static power consumption of the processor is dominant in the low-frequency application scenario where the operating frequency is below 1 MHz.A design scheme is proposed to reduce the power consumption of the system by dynamically turning on and off the power supply of each circuit module in the processor according to the instruction type.First,a no-pipeline processor is designed based on the RV32EM instruction set,and its logic synthesis is performed using TSMC 65nm process.Through the analysis of power consumption,the total power consumption of the processor below 1MHz is dominated by static power consumption.Based on this,an equalization system clock cycle processor is proposed,and the power gating technology is used to turn on the power supply of each stage of the circuit step by step during the operation of the processor.Synopsys low-power design flow is used to implement low-power verification synthesis and power consumption analysis for the design.Analysis of the power consumption results shows that the total power consumption of this architecture is reduced by 40%compared to the no-pipeline processor when the operating frequency is 1 kHz.Then,on the basis of equally dividing the system clock cycle processor,taking into account the excess execution time allocated to each stage of the equally divided system cycle,a design proposal is proposed to shorten the necessary execution time of the processor but leave the turn-on and turn-off mode unchanged.That is,the instruction operation is completed in as short a time as possible,and then the logic circuit other than the fetching module is turned off.As a result,Analysis of the results shows that the power consumption is further reduced,which is 81%lower than the total power consumption of the no-pipeline processor at the operating frequency of 1 kHz,while the applicable frequency range is increased from 500 KHz to 700 kHz.Finally,by introducing the concept of instruction classification,the design is divided into fine-grained modules,and the power of each logic circuit module included in the "execute"level of the processor is turned on and off according to the instruction function.The power analysis results show that the design consumes 81%less power at 1KHz than the no-pipeline processor,but the applicable frequency range has increased from 700KHz to 1MHz for the second structure.Therefore,this design is suitable for low-power applications with operating frequencies below 1MHz,which can effectively reduce the static power consumption of processors in low-speed and low-process nodes and meet the design goals.