Way-Access Track And Way-Doze Based Low Power Cache

As integrated circuit manufacture process enters deep sub-micron and extra deep sub-micron age, the integration level doubles continuously with ever-increasing chip speed and performance. With the number of transistors on a chip keeping being larger, the energy dissipation is going higher. Low power and high performance embedded microprocessor will be a must for portable and mobile devices in future. A low-power instruction cache based on way-access track and a low-power data cache based on way-doze are presented in this paper.A low power set-associate instruction cache based on way-access track is proposed to relief the energy consumption of instruction cache. Redundant tag checks and accesses of unrelated data are eliminated by establishing way-access track record in modified instruction cache and branch target buffer. Various way-access track record maintaining strategies is proposed to reduce reestablishment of track record, which improve the utilization of these records. Experiments show that, compared with traditional instruction cache, way-access track cache achieves a reduction of accesses of tag and data, which is only 2.40% and 26.80% of traditional instruction cache.A low-power data cache based on way-doze is proposed to relief the energy consumption of data cache. Use gated-power-source technology to switch off long-term unutilized cache lines and leakage energy of these cache lines is saved. Moreover, various applications are studied for optimum doze thresholds. Then a configurable global doze threshold register is proposed for meet different threshold requirements of different applications. Experiments show that, in best cases, leakage energy of data cache lines is only 9.13% of traditional data cache. This ratio, in worst cases, still remains 34.7%.