A 9bit 125mhz Pipelined Adc Design,

Recently, video signal processing technology experiences a rapid development, which raises higher requirement in one of its critical circuits ---- analog-to-digital converter. As a general analog-to-digital interface, ADC is widely used in mixed signal circuits. Due to the development of digital signal processing technology and integrated circuit technology, ADC is developing to the phase of higher performance, for example, higher conversion speed, higher resolution, lower power dissipation, smaller area.Based on full-custom, top-down integrated circuit design method, this paper presents a high performance and low power dissipation ADC, used as the analog-to-digital interface of HDTV chip. After analyzing the basic principle of A/D conversion, drawing a comparison among different kinds of ADCs and taking consideration of the requirement of ADC in video system, this paper selects pipelined architecture as the ADC architecture. Compared to other ADC architectures, pipelined ADC can achieve high conversion speed as well as high resolution. Trading off between speed and power dissipation, 8 stage, 1.5bit/stage pipelined ADC architecture is adopted to accomplish this 3.3V, 125MHz, 9bit ADC.In order to ensure the validity of pipelined ADC architecture and algorithm, system modeling tool----Simulink in Matlab is used to make a system simulation of pipelined ADC before designing of circuit. This guarantees the effectiveness of system architecture, and also evaluates all of the error sources that may affect ADC output result.In cadence design environment, based on TSMC 0.35um 3.3V CMOS model, this paper designs and simulates all of the circuits which consisted in ADC. The paper analyzes and designs the following sub-circuits and functional circuit blocks: (1) Non-overlapping clock circuit. It is used to control the time-consequence of each stage of pipelined ADC. (2) Analog switch. CMOS complementary switch, instead of NMOS switch is used in switch-capacitance circuit. (3) Operational amplifier. Operational amplifier is the key part of ADC. It is the PMOS transistors input, folded cascade architecture. Simulation result shows that its gain is 91 dB, bandwidth is 450MHz and slew rate is about 500V/us. (4) Comparator. High speed, low power dissipation comparator is designed in this paper. It can operate at 125MHz with low static power dissipation. (5)Sample and hold amplifier. It is the first stage of pipelined ADC; it samples the input analog signal at one clock cycle and holds it at another clock cycle. (6) Multiply digital to analog converter. It is used in the second to eighth stages of pipelined ADC. It has four functions which are D/A conversion, subtract, 2 gains amplify and sample&hold. (7) Delay register array. It is used to ensure the digital codes resolved by each stage export to digital-correct-circuit at the same time. (8) Digital-correct-circuit. It sums all of the digital codes resolved by each stage, and exports conversion results. (9) Output latch. Latch conversion result. (10) Reference circuit. Bandgap technology is used to obtain reference voltage and current.Completed all of these circuits, the paper import ramp and sine signal to ADC to simulate and test the whole circuit. The simulation result shows that, at the sample frequency of 125MHz, when input ramp signal, the output of ADC is correct, INL is less than 1LSB, DNL is less than 0.6LSB; when input sine signal, the paper get the performance parameters by taking Fast Fourier Transfer of the ADC output result. These parameters are listed as follows: SFDR is about 70dB, SNR is great than 55dB, THD is about -60dB and ENOB is about 8.8 bit. However, power dissipation less than 100mW.