The Design Of Pipeline-SAR ADC Based On 0.18um Process

Today, people can not live without a variety of electronic devices such as smart phones, tablets, and personal computers, etc. Emerging various electronic devices in the rapid development of the Internet of Things today are endless, such as smart wristbands and smart aircraft and the like. Modern electronic equipment is essential to all kinds of integrated circuits, integrated circuits, various functional elements integrated on a silicon substrate to achieve system-level functions on a small area. Since the integration of electronic devices become more sophisticated, so in many applications of electronic systems, integrated power electronic systems become the main source of power. The integrated circuit process technology as Moore’s Law, as feature sizes continue to decrease, the number of transistors per unit area doubled. IC feature sizes decrease makes it to further improve the integration of integrated circuits and circuit by improving infrastructure to further reduce system power consumption. However, the real world is analog signal is present,the analog signal relative to a digital signal in terms of a few special properties,such as signal spectrum tends to infinity, the signal changes irregularly and so on. To be able to high-technology digital processing stability and ability to deal features applied to the analog domain, analog to digital converter as a bridge appeared. ADC contains a variety of modern architecture, such as Sigma-Delta ADC, Pipeline ADC, SAR ADC Flash ADC and so on. However,since the basic principle of ADC limitations of each ADC can only play a role in specific application areas. Among them, since the pipelined ADC ADC good compromise between power consumption, conversion rate and conversion accuracy three performance indicators, has become the mainstream architecture high-speed, high-precision analog to digital converter.This paper introduces the basic principles of pipelined ADC, the establishment of a 14 bit Pipeline ADC model 2.5bit / Stage, and this model system simulation analysis while the sub-circuit pipeline ADC for power analysis. Then, the paper introduces the MDAC design based on the comparison and the current source, while a 1.5bit / Stage using dual comparator and a current source architecture MDAC MDAC example to introduce this method and design requirements, and gives the transient Simulation results. Then, introduced 14 bit Pipeline SAR ADC components and circuit functions, from the three-part introduction to start, one asynchronous clock successive approximation ADC design, the other is a sample and hold circuit design, and finally the first an MDAC circuit design. Finally, the paper describes the simulation results for Pipeline SAR ADC for each part of the circuit, including asynchronous clock FFT results SAR ADC simulation results and 14 bit Pipeline-SAR ADC’s.In summary, this paper from two angles to explore the development of Pipeline ADC, a comparator and a current source with a combination of alternative ideas operational amplifier, and the other is the use of high gain MDAC and asynchronous clock successive approximation analog to digital converter(SAR ADC) a combination of methods. This paper designed a Pipeline-SAR ADC, the input signal frequency of 1.22 MHz under the conditions, the sample holder effective number of bits(ENOB) is 14.8bit,overall ADC SNR simulation results(SNDR) of 73.2d B, effective number of bits is 11.9bit.