Search And Design Of A C-2C Saradc Applied In PLC System

System-on-a-chip (SoC), which has been an extramly popular application incommunication, has been expected to meet the demands of area reduction and powerefficient, owning to the reality that the communication equipments have been tendingto be lower-cost and lower-power-consumption. One of the important parts of almostall SoCs is the Analog-to-Digital Converter (ADC), which acts as the interfacebetween the analog-front-end and the digital signal process. The low-area andlow-power-consumpation design of the ADC makes a lot of sense in building a SoC,while it has been meeting much more challenges for the reasons that the CMOSprocess technology is continuously scaling down yet the specifications of the ADCskeep higher and tougher.With the background of power line communication and the target of being usedin the remote transcribe system, a Successive Approximation Register (SAR) ADCwhose resolution is10-bit, sampling rate is5MHz, demanding ENOB is more than9-bit, demanding SFDR is higher than70dB and current power-consumpation is lessthan100Ais designed, based on SMIC0.18μm CMOS process in this thesis.The main line of the thesis is reducing area and power consumpation, and thetwo functions of ADCs are discussed first.The structure and the work process of SARADC are showed afterwards, followed by an extremely close analysis of area andpower issiues in traditional Charge-distributed Digital-to-Analog Converters (CDAC)which are popularly used in today’s SAR ADCs, then the designed C-2C CDAC is putforward. The design of this C-2C CDAC has begun with plenty of analysis intheoretical perspective, including the calculation of the unit capacitor value and theselection of the capacitor type, based on the consideration of noise issue and matchingissue. The circuit of the proposed C-2C CDAC is built and simulated after two stepswhich are designing the bootstrapped switches and getting the switches and thecapacitor array together are done. What’s more, a new latch comparator with apre-amplifier which consumes quite a little power and the logic circuit that combineswith the C-2C CDAC to realize the successive approximation algorithm are alsodesigned. Layout of the SAR ADC is carefully planned after the building and thepre-simulation of the whole. Post-simulation is done as well and the result shows thatwhen the input frequency is1.12347MHz and the sampling rate is5MHz, the ENOBand the SFDR of the SAR ADC is9.46-bit and70.3dB, separately. The total powerconsumpation is about55.4A.All of these entirely meet the specifications which arerequired from the application system.This thesis shows an insight into the theory analysis and the circuit design of the C-2C CDAC as well as a lower-power comparator. The layout plan is also done basedon several elaborations. It might be a helpful reference in lower-power SAR ADCs’design.