The Research And Realization Of A 12 Bits 50 MSPS Low Power Pipelined Analog-to-Digital Converter

As a bridge connecting the analog signal and digital signal, the demand of the high-performance analog-to-digital converter has growing rapidly with the digitalization of the circuit system, especially the rapid development of the system on chip. Compared with other structures, the pipeline ADC has a good favor because of its good compromise between the high resolution, high speed and low power consumption. In this thesis, a 50MSPS, 12bit ADC was designed in dongbu 0.13um process.Access to a large number of documents, this paper completes the design of each module circuit and the overall circuit step by step with the goal of high speed, low voltage and low power consumption, according to the Analog IC design flow. The main work of this paper is as follows. Firstly, completing the circuit design of the two-phase non-overlapping clock generator; the bootstrapped switch, which can eliminate the switch charge injection error; the gain enhanced folded cascode operational amplifier, which can ensure the speed and accuracy of the switch capacitor circuits, and the dynamic latch comparator. Secondly, completing the circuit design of each sub-module by the unit circuit, and simulating each module and the overall system in detail. Thirdly, in order to reduce the power consumption of the system, scaling down technique of the capacitor and operation amplifier was used, and a digital calibration circuit was designed to overcome the comparator offset error.This design works in the Cadence platform, the simulating tool is Cadence Spectre. The simulating results show that, with a power supply of 1.2V, the input voltage range of the ADC is between 0.4V and 0.8V, its resolution is 12 bits and sample rate is 50MHz, the power consumption is about 84mW. The parameters of this pipeline ADC meet the design requirements.