Design Of Wideband Frequency Divider Used In Radio Frequency

With the high-speed development of the wireless communication systems and other relevant fields, more wireless communication standard protocols have been widely used, resulting that research and design of multi-mode communication chips have attracted more and more attention. In multi-mode communication system, a difficulty of this circuit is the design of the frequency synthesizer (FS), which enables to provide high-accuracy and high-stabilization signals as the standard reference frequency. In phase-locked-loop (PLL) based FS, the frequency divider is one of the most important blocks, which makes FS possible to provide high-precision frequency signals while reaching high operating frequency and low power consumption.Firstly, we summarize the principle of the PLL-based FS and how it works, and analyze its linear model briefly. Secondly, a comprehensive summary and comparisons of frequency dividers are presented, which includes various structures of triggers and their merits and drawbacks in performance.Then, this thesis mainly describes a programmable divider based on the pulse-swallow counter and a multi-modulus divider based on cascaded divide-by-2/3 cells, including the operating principles and basic structures.Used in L-band multimode wireless communication receiver, this thesis presents a design of programmable divider baesd on the pulse-swallow counter in 0.18-μm CMOS process, including its pre-simulation, layout and post-simulation. Its modulus can be varied from 128 to 511. The post simulation shows that the programmable divider can operate well over a wide range of 2-4 GHz. The core circuit without test buffers consumes 3.69 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.0182 mm2.Finally, the high-speed multi-modulus divider is designed based on cascaded divided-by-2/3 cells in 90nm CMOS, the modulus of which can be varied from 16 to 31. The post simulation shows that the programmable divider can operate well over a wide range of 4-8 GHz under a 1.2-V supply voltage. The core circuit occupies a chip area of approximately 1.46×10-3 mm2.As a new hotspot in the wireless communication, the design of programmable divider and high-speed multi-modulus divider used in L-band multimode wireless communication receiver has not only engineering application value but also prospect of broad market application.