Research On Key Circuits Of 8GHz Fractional Frequency Synthesizer

In the field of wireless communication,RF transceiver has always been a research hotspot,which has been widely used in mobile radio communication base station,FMCW radar system,wireless LAN,Wi MAX and other fields.As one of the important modules of RF transceiver,frequency synthesizer is mainly used to generate local oscillation signal of specified frequency for receiving and transmitting signal.As people have more demands on the performance of electronic products,low noise has become one of the most important performance indexes of frequency synthesizer,and it is also one of the development directions of frequency synthesizer at present.This paper designs a low noise 8GHz fractional frequency synthesizer chip based on this demand.The main contents of this paper are as follows:1.The basic structure and working principle of Phase Lock Loop(PLL)are introduced and analyzed,its linear model and transfer function characteristics are further deduced,and important performance indicators of PLL in frequency synthesizer application are introduced.2.The main circuit modules of the charge pump phase-locked loop are studied in detail,the noise characteristics of the system and each module are analyzed,and the phase noise transfer function of each module to the system is derived,which provides theoretical support for the following circuit design;3.Two innovative structures are proposed in this paper:a low noise charge pump,which reduces the phase noise of the system output signal by increasing the charge pump current in the optional low noise mode to reduce the contribution of the charge pump to the system phase noise.After theoretical deduction and simulation test verification,this structure can reduce the phase noise of about 3.2d B;A programmable high speed frequency divider which can extend the range of frequency divider is introduced.By adding a 15 bit programmable decrease counter on the basis of the traditional 2/3 multimode frequency divider cascade programmable frequency divider,the range of frequency divider of the high speed frequency divider can be adjusted from16 to 2¹⁹-1.At the same time,a reference signal path input buffer and a high-speed signal path input buffer structure are proposed to meet the requirements of the system,which can perform level conversion,impedance matching and provide suitable driving ability for external input reference and feedback signals.4.Before and after simulation verification of PLL system and each module is carried out in Cadence/Spectre simulator,layout design of key modules proposed in this paper is introduced,and test results are analyzed.The proposed frequency synthesizer is designed by 0.35?m Si Ge Bi CMOS process.Simulation results show that the output phase noise of the circuit is only-112.9d Bc/Hz(8GHz input,fractional frequency division mode,50KHz offset)at the operating voltage of 3.3V,and can be locked at the highest frequency point of 8GHz.The core chip area is 4mm~2.