Researchof The Key Modules And Compiler Forlow Voltage SRAM

With the rapid development of mobile Internet, The requirementof processing speed and standby timeof portable mobile intelligent terminal is also increasingly high.As a data storage tool,memory is widely used in mobile devices.Typically, the area of memory chip is more than half of the whole system chip. So it has an important influence on the performance of the whole system chip.The working conditions of SRAM in low voltage will directly affect the function of SoC. Therefore, research how to reduce the power consumption of the memory is very important.For static random access memory (SRAM), with the progress of technology, the influence of the process deviation of the circuit is more and more big. The influence is mainly manifested in two aspects:one is the serious deterioration stability of traditional 6T SRAM under low voltage, and the other is deteriorative timing delay. In order to solve the problems a low voltage SRAM and a SRAM complier are designed. The main contents of the dissertation are summarized below.(1) Describe the structure and basic working principle of SRAM, analysis the problems of SRAM under low voltage, such as static noise margin(SNM) degradation, limited number of cells per bitline, poor writability and the impact of process variations. Then, analyze the existing low voltage SRAM technology.(2) A 12 tube SRAM cellis proposed. This SRAM cell can work stable in near/sub-threshold voltage. Under the 400 mv supply voltage, compared to the traditional 6 tube SRAM cell, read static noise margin and hold static noise margin of the proposed SRAM cell is improved respectively 82% and 41.67%. At the same time, considering the process variationeffects ofcircuit layout design, analyzed the effect of each transistor if there is a threshold voltage deviation. Then, we propose a circuit layout design methodof 12 tube SRAM cell.(3) A new current-mode sense amplifier combined with leakage current compensation is proposed. The leakage current compensationcircuit provides the corresponding positive feedback path automatically for the main circuit based on the different slew rate of the signals. Then the compensation purpose can be achieved. Compared with the traditional current sense amplifier the proposed sense amplifier reduces 42.90% delay time under low power voltage.(4) Combine with the constant proportion design method, a two-stage decoding circuit is designed based on single edgeoptimization model. In order to decrease the effects of process variation, a digital double replica-bitline technologyis proposed. Under the condition of 27 degrees,0.8 V power supply voltageand tt process angle, the proposed technology reduces 61.03% process variationcompared with traditional replica-bitline technology.(5) Analysis the influence of modeling and joint method of SRAM compiler, and design a SRAM compiler. Then, generate four low voltage SRAMs (512*8,512*32, 16*2,8192*128).At last, tape out these four chips and test them.