Research And Realization Of Timing Control Circuit For Wide-Voltage Static Random Access Memory

In recent years, with the rapid popularization of mobile Internet devices, the requirements for the performance and power consumption of mobile processors are becoming higher and higher, and the dynamic voltage regulation technology is good for this two advantages. But as an important module of mobile processor:static random access memory (SRAM), when the SRAM work at wide voltage, there are two important problems in the design of timing control circuit:First, at low voltage, the local process variation lead to big timing circuit delay variation, this increase the critical path delay and reduce the chip performance, Second, because of the poor voltage tracking characteristic of traditional timing control circuit, when the voltage level changes, SRAM read error.In order to solve these two problems, firstly, this thesis illustrates the impact of timing control circuit to the SRAM read critical path. We analyze the timing control circuit in wide working voltage under process impacts. The traditional timing control circuit and the existed several improved timing control circuit design methods are also analyzed in detail. Then this thesis proposes a wide voltage replica bitline technology. This technology is divided into two parts:A, we discharge the parallel local replica bitlines at the same time, effectively reduce the local process variations caused by timing circuit delay variation, compared to the existing replica bitline technology, this method does not increase any additional delay and improve the reading performance. B, the delay tunable replica bitline based on BIST test technology has been proposed. This technology ensures the SRAM has the best performance at the wide power supply voltage. Realize the tracking of the voltage. Compared with the traditional adjustable inverter chain, this method has a better temperature tracking and do not increase any layout area.Based on 40nm CMOS SMIC technology, this thesis is involved in the completion of a 64Kbits wide voltage SRAM design is responsible for the completion of the timing control module design. Simulation and test results show that, at 0.6V, compared to the traditional timing control circuit, the timing circuit designed proposed in this thesis reduced delay variation by 71%, compared to the traditional timing control circuit, the overall SRAM using the design of this thesis reduced the SRAM delay by 17.2% at 0.6V.