Full Custom Design And Realization Of Static Random Access Memory IP Core

With the development of SOC design method based on IP core,the need of reconfigurable IP core increases.Because SRAM comes up low power characteristic, Static Random Access Memory is the most common and important memory component in CPU and other electronic products.At present,SRAM complier can generate different capacity SRAM conveniently and quickly,but its performance can't reach high-speed and low-power goal in high performance microprocessor.So,it is significant to design a low power and high speed SRAM by full custom design method.For reducing design cost,the designed circuit module with reconfigurable characteristic is necessary.The proposed 16Kb SRAM IP core with reconfigurable input and output data bitwidth is implemented in 0.18μm CMOS process.The structure design,circuit design, layout design,BIST design and IP modeling of IP core are finished,at the same time, the SRAM after taping out is verified.This SRAM with proposed reconfigurable decoder structure can input and output 64 bits and 128 bits data width without changing the design.The design idea guide SRAM complier design.Besides,this paper researches on low power design method of SRAM complier which is based on H-tree structure and optimizes a kind of current mode amplifier,its power consumption is only 77%of Latch structure amplifier's.In typical case that the work power supply is 1.8v,the delay of writing data in SRAM is less than 1.35ns and the delay of reading data is less than 1.54ns,Under the condition of 500MHZ clock frequency,the average power consumption is 35.053mw. Comparing to the SRAM generated by the memory compiler in the same process,the designed SRAM's average power consumption reduces by 20%,and the access time reduces by 10%.