| X DSP is a 32-bit fixed-point DSP chip being designed. Its architecture is VLIW and it can issue 8 instruction in a cycle and deliver as much as 4800MIPS,It runs at a frequency of 600MHz. It is necessary for the SRAM of L1 Cache to run at the same speed with the processor. However, the SRAM's designed by the Memory Compiler can't reach high-speed goal. So, it is significant to design a high-speed SRAM by full custom.The main contents of this paper are as follows:Firstly, based on the requirement of L1 Cache. I design the structures and timing of the SRAM. The memory, decoder and sense amplifier circuit are designed and optimized. The current-mode sense amplifier can improve the performance of SRAM effectively. The layout simulation, using HSPICE, has been carried out to verify its speed is 24% faster than the original current-mode sense amplifier and 46.1 % faster than the conventional voltage-mode sense amplifier.Secondly, make the floorplan during designing the layout. Determine the bit array which is important to the area of the SRAM and expand the other module along the vertical and horizontal, until all modules are placed. In the memory array, two bit cell are made as a module, reducing the capacity of contact and area of the layout.At last, all modules which are for IP modeling are set up. The scan-test circuit is designed for verify the performance. By intercepting lots of test-vector from the VCD file. The layout simulation, using nanosim, has been carried out to verify the SRAM can work at 750MHz at typical environment, can work at 600MHz at worst environment.In the normal temperature, the layout simulation results show that the deode-time of SRAMs is 544.6ps, and the read-time is 827.2ps at 600MHz. Our design's requirements have been fulfilled. Compared to the SRAM(which is generated by the memory compile),the designed SRAM's read -0-time reduces by 26.1%,write-1-time reduces by 27.9%,write-0-time reduces by 26.2% and the average power consumption readuces by 15%。... |
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