Research And Design Of Noise-Shaping SAR ADC With Dynamic Element Matching

Data converters play an important role in the conversion of analog and digital signals,serving as tools for communication between the analog and digital worlds.With the continuous iteration of technology and the upgrading of market demands,designers have put forward higher requirements for various aspects of the performance of data converters.Among them,the analog-to-digital converter(ADC)has become a focus and challenge in both academia and industry due to its relatively complex structure.The successive approximation register(SAR)ADC has advantages such as low power consumption and the ability to adapt to advanced processes due to its simple structure and high level of digitization.However,the problems of DAC capacitor mismatch and comparator noise in SAR ADCs limit their resolution to typically below 12-bit.The sigma-delta ADC achieves high signal-to-noise ratio through oversampling and noise-shaping techniques,but the use of an active loop filter and high oversampling rates results in high power consumption and a low signal bandwidth.The noise-shaping SAR ADC is a new ADC structure in recent years,combining the advantages of SAR ADC and sigma-delta ADC,with high accuracy,low power consumption,and the ability to adapt to advanced processes.This paper focuses on the research and design of the noise-shaping SAR ADC,with the following main research content and innovations:(1)A survey was conducted on the development and research status of noise-shaping SAR ADCs,and the two mainstream architectures of cascade integrator feed forward and error feedback were analyzed and derived in detail.(2)A second-order noise-shaping SAR ADC with passive gain was designed.The integration capacitors in the loop filter are connected in series and passively amplified in the SAR conversion stage at the input of the multi-input comparator,reducing the requirements for the comparator gain.By performing two integrations of the residual voltage on the DAC capacitor array,second-order shaping of the quantization noise is achieved,enhancing the noise-shaping ability of the SAR ADC.During the SAR conversion stage,the DAC capacitors and integration capacitors are separately connected to the input of the multi-input comparator,avoiding the impact of channel charge injection from the MOS switches on the noise shaping SAR ADC.(3)A segmented dynamic element matching(DEM)circuit based on the weight bit rotation method was proposed to address the problem of DAC capacitor mismatch in noise-shaping SAR ADCs.By selecting DAC capacitors through weight bit rotation,a very simple buffer can be used instead of a more complex binary-to-thermometer decoder,reducing the scale of the DEM circuit.In addition,using a segmented DEM circuit for the DAC capacitor array avoids the problem of exponential complexity growth of the DEM circuit.(4)The layout of the noise-shaping SAR ADC was designed,and parasitic parameters were extracted for post-simulation.The simulation results show that the noiseshaping SAR ADC achieved an effective number of bits(ENOB)of 14.8-bit with a signal bandwidth of 50 k Hz and power consumption of only 231μW,achieving a Schreier figure of merit of 174.5d B.