Research And Design Of Low-power Successive Approximation ADCs

As a bridge between analog and digital signals,the Analog-to-Digital Converter（ADC）has wide applications in many fields,including wired/wireless communications,biomedical devices,and measurement instruments.However,wireless sensing networks using conventional ADCs are more cumbersome to operate due to their high ADC power consumption,which leads to shorter battery power supply time and lower operating efficiency of such devices,requiring frequent battery replacement.The successive approximation ADC is a popular type of ADC,which not only has the advantages of simple structure,easy implementation,small area,and ease of integration but also has relatively low power consumption.The research goal of this article is to further optimize the power consumption performance of the successive approximation ADC.The main work is as follows:Firstly,the mainstream structures of ADCs are analyzed to design a successive approximation ADC with better performance.A comparison of the working principles and performance parameters of different types of ADCs is conducted,and their application scenarios are described.In addition,to obtain a low-power SAR ADC,the basic structures of digital-to-analog converter（DAC）,hold/sample switches,comparators,and logic control circuits are analyzed,along with the factors that affect their performance.Secondly,based on the V_cm-based switch switching strategy,the DAC capacitor array structure is improved.In order to reduce the total capacitance value and reduce circuit power consumption,the DAC capacitor designed in this paper adopts a fully differential input structure,which can effectively suppress common mode interference,and the last three weight capacitors of the DAC capacitor array are designed to be composed of two or four capacitors of the same capacitance in series.Compared with the V_cm-based switch switching strategy,the improved DAC capacitor array reduces the total capacitance by 75%,effectively reducing the circuit power consumption and saving chip area.Finally,improvements are made to the preamplifier and latch to reduce the influence of static power consumption.A new type of gate voltage bootstrap sampling switch is used to ensure that the gate-source voltage of the bootstrap switch is always constant and to reduce the switch nonlinearity.Based on the TSPC-improved logic control circuit,signal division and control of the DAC capacitor array switches are achieved,ensuring the normal operation of the SAR ADC according to the timing sequence.This design is based on CMOS 180nm process for 10-bit successive approximation type analog-to-digital converter.The simulation results are:when the input signal voltage is 1.8V and the frequency is 2.890625MHz,the effective bit count ENOB is 9.84bit,SNDR is 60.98d B,SFDR is 72.91d B,and the average power consumption is 88.72μW.