| The rapid development of integrated circuit manufacturing technology and digital signal processing techniques has propelled the advancement of information processing towards digitalization.Natural signals such as light,electricity,sound,and temperature are continuous analog signals,while digital circuits require discrete digital signals for processing.To achieve the conversion from analog to digital signals,the analog-to-digital converter(ADC)is developed and plays a critical role in signal processing.With the increasing diversity of requirements,ADC design faces challenges of high speed,high precision,and low power consumption.The successive approximation(SAR)ADC stands out among many ADC structures due to its simple circuit structure,high speed,and low power consumption.In this thesis,based on the XFAB 0.6μm CMOS standard process,a segmented SAR ADC with 12-bit accuracy,1 MS/s sampling rate,and 8-channel selection is designed in this study.In the sampling switch design,substrate potential-following source potential technology is employed to improve the accuracy of the sampling switch.In the capacitive digital-to-analog converter(CDAC)design,a "7MSB+5LSB" segmented structure is proposed for the 12-bit CDAC,and only the high MSB capacitor array participates in the sampling of the analog input signal,while the low LSB capacitor array does not need to participate,effectively reducing the circuit power consumption.Compared with traditional single-stage capacitor arrays,segmented capacitor arrays significantly reduce the total number of capacitors,and bottom plate sampling can avoid channel charge injection effects,improving the accuracy of the SAR ADC.In the comparator design,a single-ended comparator structure based on an inverter is proposed.Compared with a fully differential comparator,the single-ended comparator designed in this thesis reduces the matching requirements of the circuit,and only requires a single CDAC capacitor array,greatly reducing the difficulty and area of chip design.When designing the analog frontend channel selection circuit,a scheme is proposed that can support multiple input analog voltage conversions for 8-channel selection.The post-simulation results of the overall 12-bit SAR ADC circuit,under the conditions of an analog power supply of 5 V and a digital power supply of 2.4 V,inputting a full swing sine wave signal of frequency 467.77 k Hz and a sampling frequency of 1MHz,indicate that the maximum DNL is-0.64/0.89 LSB,the maximum INL is-0.70/1.05 LSB,the SFDR is 77.42 d B,SNDR is 67.06 d B,and ENOB is 10.85 bits.These results demonstrate that the SAR ADC meets the design requirements. |
