Design Of Phase-locked Loop For USB2.0 Application

In the digital communication and high speed transceiver field, clock and data recovery circuit is widely used. Providing a low jitter, process independent clock to the receiver is a very important part.This study is trying to design a completely monolithic phase-locked loop (PLL), which is used for usb2.0 clock generation and NRZ data recovery application. The design work is from top level design to all the bottom blocks, including Phase detector, Charge Pump, Low pass filter, VCO and other auxiliary circuits by TSMC 0.18um CMOS process and 3.3V power supply.The paper describes the PLL system theory, cell circuit design and simulation, and loop simulation. All the simulation results satisfy high speed USB2.0 spec.