Design Of High Precision Successive Approximation Register Analog-to-digital Converter

In recent years,many emerging applications such as data acquisition systems and medical imaging systems require integrated analog-to-digital converters with high accuracy.SAR ADC is suitable for CMOS integration,and provides a nice compromise among sampling rate,conversion accuracy,power consumption and design complexity.Thus,SAR ADC is suitable for these applications.In this thesis,the module of comparator,analog-to-digital converter,SAR logic and the capacitor mismatch calibration technology are studied,and a 16-bit 2.56 MSPS high-precision SAR ADC is designed.Firstly,this thesis proposes an improved two-stage dynamic comparator,which effectively reduces the power consumption of the comparator.And a full-dynamic offset correction circuit is designed,which reduces the input offset voltage of the comparator to less than LSB/2 by introducing unbalanced load capacitors at the output of the preamplifier.Secondly,segmented capacitor array and common-mode based switching method are adopted to reduce the number of capacitors and the power consumption of CDAC.In the MSB section,a non-binary capacitor array with redundancy is designed to correct the error caused by incomplete CDAC voltage establishment and unstable reference voltage.In addition,dynamic SAR logic is proposed to shorten the delay and reduce the power consumption of SAR logic.Moreover,a calibration technique that combines “split ADC”-based digital calibration and perturbation-based digital calibration is proposed,which only requires to add capacitors into the capacitor array,without complex analog circuits.A 12-bit,512 k SPS SAR ADC has been taped and mearsured previously.The mearsuring results show that when the sampling frequency is 512 k Hz and the input signal frequency is 11.21875 k Hz,the SFDR is 67.7 d B and the SNDR is 59.6 d B.The DNL and INL are within-1/+1.71 LSB and-3.75/+4.44 LSB,respectively.Based on the 12-bit SAR ADC,the circuit and post-simulation of the proposed 16-bit SAR ADC are implemented in the 180 nm process.The post-simulation results show that when the reference voltage is 5 V,the sampling frequency is 2.56 MSPS and the input frequency is 1.1675 MHz,the SFDR,SNDR and THD after calibration are 105.4 d B,93 d B and–101.2 d B,respectively.The DNL and INL are within-0.6/+0.55 LSB and-2.48/+2.15 LSB,respectively.All of these performances meet the target specifications.