Design Of Low-Power Dual-Channel Pipeline ADC

Triggered by the rapid development of portable terminal devices,chip design requires higher efficiency and lower power consumption.The analog-to-digital converter(ADC)is one of the most widely used core chips.Low-power,small-area designs based on it have recently seen a surge of demands.However,in view of sub-micron processes,the high-performance circuit design becomes more and more sophisticated.The pipeline analog-to-digital converter is a mainstream architecture for high-speed,high-precision design,and its low-power optimization has been receiving significant attention.On the basis of traditional pipeline architecture,this thesis proposes a low-power dual-channel pipeline ADC.Initially,the basic principle and conversion algorithm of pipelined ADC are analyzed.In light of the synthetical consideration of performance indicators such as area,speed,power consumption,and previous researches on general low-power technology,the system architecture of low-power pipelined ADC based on low-power measures without sample-and-hold circuit and operational amplifier sharing is demonstrated.According to the system architecture and module circuit requirements,circuits for core modules are designed,including operational amplifier,dynamic comparator,first-stage MDAC and first-stage sub-ADC.By adopting the GSMC0.13?m CMOS process,layouts of core module circuits are completed with Cadence Virtuoso.Depend on the models from process library and the Cadence Spectre simulation tool,the core circuit of the proposed low-power dual-channel pipeline ADC has been simulated and verified.Results show that the low-frequency gain of designed operational amplifier is 124dB,and the unity-gain bandwidth is 405.3MHz.With a2.5MHz sampling frequency,when a sinusoid signal which is generated with input voltage of 0~3.3V and frequency of 17.08984375KHz is input,the ENOB of the converter turns out to be 11.8 bit,the SNR is 72.7 dB,the SFDR is 91.4 dB,the overall power consumption is about 40 mW,and the size is 1.2×1.3 mm~2,satisfying the device requirements well.