Design Of A 10-bit Wide Power Supply Voltage Range SAR ADC

Successive Approximation Register Analog-to-Digital Converter,As a sensor signal processing and battery management system,SAR ADC is widely used in automotive electronic systems,industrial control and portable equipment.Automotive electronic systems often need to work under harsh environmental conditions.Because of load fluctuation,power supply fluctuation,external interference and other problems in industrial control system,the power supply voltage is often unstable;Portable devices are usually powered by batteries whose voltage fluctuates with time of use and the load on the device.In these scenarios,SAR ADC is required to maintain stability and accuracy in the face of large power supply voltage fluctuations.In this thesis,according to the requirements of medium-speed applications in a wide range of supply voltages,a 10-bit SAR ADC is designed to operate at 2.3V to 3.3V.The sampling rate is 20MS/s when the supply voltage is 3.3V and 14MS/s when the supply voltage is 2.3V.In order to solve the problem of low supply voltage sampling rate decline,this design uses a hybrid capacitor resistance array,which effectively reduces the total capacitance area and improves the sampling rate.The comparator consists of a two-stage preamplification stage and a one-stage latched comparator.Since the response of the preamplification stage is logarithmic in the small signal interval,the response of the latched comparator is exponential,this structure can significantly improve the response speed of the comparator.In addition,a cascade of misalignment is used to ensure the accuracy of comparator judgment.This design uses a reference current source circuit unrelated to the power supply voltage to provide a stable reference current for the comparator,to ensure that the comparator can still work normally when the power supply voltage is reduced.In order to meet the requirements of medium-speed applications,an asynchronous logic is designed,which is the master control logic and the DAC control logic respectively.The master control logic determines whether to complete the comparison and proceed to the next step based on the various states generated by the standard processing.The DAC control logic generates the corresponding DAC control signal according to the comparator output.By proceeding to the next step according to whether or not each module is completed,the synchronization logic’s invalid wait time is avoided,thus improving the overall circuit speed.The circuit simulation is based on TSMC 40 nm CMOS technology.The simulation results show that the sampling rate of each Process corner reaches 20MS/s at 3.3V power supply voltage.The ENOB of TT Process corner is 9.91,SNDR is 61.42 d B,and the power consumption is 6.24 m W.At 2.3V power supply voltage,the sampling rate of each Process corner reaches 14MS/s.The ENOB of TT Process corner is 9.90,SNDR is 61.39 d B,and the power consumption is 2.16 m W.