Research And Design Of High Precision And Low Power SAR ADC

Nowadays,more and more multitudinous information in nature are received by people.These information are received and used in the form of signals by people.So the importance of signal processing system in daily life is increasing day by day.As an important role in the signal processing system,Analog-to-Digital Converter(ADC)link up the real world and the digital world.What’s more,it plays a vital role in the modern society.The successive approximation register ADC(SAR ADC)is widely used in medical devices,portable wearable devices and other fields because of the advantages which make the chip has lower power,smaller area with a moderate accuracy and speed.With the researcher continuing studying,people put forward higher requirements for the SAR ADC,making it develop towards higher accuracy and lower power consumption.The DAC capacitor array in SAR ADC is the main factor limiting its power consumption,and the comparator and sampling circuit will have an impact on the accuracy of the whole system.Based on this,this thesis provides a calculation method for DAC power consumption and a solution for comparator misalignment,and proposes corresponding design solutions based on the design objectives of this article.Aiming at the problem that the capacitance of the traditional DAC which includes many capacitors and high power,a segmented capacitor array based on the common mode level switching strategy is designed,which greatly make the number of capacitors decreased.What’s more,it also can reduces the chip area and the power consumption in the process of capacitor switching.In addition,thesis uses capacitance splitting to avoid additional power consumption caused by common mode voltage.As a result,the overall power consumption of the DAC capacitor array was reduced by 55%.The whole circuit adopts asynchronous timing,and directly generates the working clock of the comparator through the circuit to avoid additional power consumption caused by the clock with a high-frequency.The bootstrap switch is used to keep the resistance of MOS unchanged which remains the input signal linear.The combination of pre-amplifier and latch improves the comparison speed of the comparator.Furthmore,the noise and offset of the comparator is suppressed by this combination.On the basis of Candence platform,this thesis designs the circuit and layout of12-bit SAR ADC in 65 nm technology.With the power voltage is 1.2 V and the sampling rate is 1 M/s,under the 98.6328125 KHz of the input signal,when the layout is verified by DRC and LVS rules,the post-simulation results show that the SFDR is71.1 d B,70.1 d B of the SNR,10.93 Bit of the ENOB and 214.6 μW of the power consumption.