The Design Of Programmable Clock Devider In SOC Based On DSP

Embedded system SOC is main solution of the IC design, integrating system on the chip is based on the advanced process. As the process become more and more advanced, SOC also getting more popular. The embedded system based DSP is used in more and more extensive area, so it’s importance for IC designer to master the DSP technology. The LSI ZSP400 is used in this project. Using which kind of bus holds the balance to implement the chip function. AMBA developed by ARM is no doubt to be a good choice. For the embedded system is mainly used in portable device, low power design is necessary in the SOC design flow. Programmable clock divider makes it come true to unify the power with the performance.The divider is programmable in this paper, DSP can access the register and modify the value in order to change the divider coefficient, so that different clocks are generated. After changing the coefficient (as modifying the register value), only after the last wave is full (as the value of counter is zero) the new efficient can be used. The burr will be a hazard to the system, so to avoid the generation of burr, negative trigger is used in the bypass circuit and latch trigger is used in clock enable. Firstly in this paper I’ll introduce this SOC architecture and then the design and verification of divider will be introduced.