Key Technologies Research Of 12.5Gb/S SerDes Receiver And High-speed Low-power Demultiplexer

With the rapid growing of information flow need, conventional parallel interface technique blocks the pace of data-transmission-rate improvement. Serial communication technology which has high speed, strong anti-interference ability and low cost is slowly replacing parallel communication technology and becomes the mainstream technology for high speed I/O interface. As one of the architectures of serial communication system,8b/10b SerDes has been widely used in Fiber Optic communication, local area network and wide area network for its providing enough message of data switch and ensuring the DC balance.SerDes receiver is consisted of two parts, namely analog circuit and digital circuit. The analog circuits are the highest rate and the most complex part among the SerDes receiver, which are mainly consisted of CDR (Clock Data Recovery) and DEMUX (Demultiplexer). The tasks of CDR extract a synchronous clock from a received high speed serial data stream, and use this synchronous clock to sample the received signal as to recover the data stream. The DEMUX can divide the recovered data stream into 10 low speed parallel data streams. The DEMUX technology in other single serial or parallel multichannel digital communications is also indispensable. With the increasing of the work rate which the circuit can be realized and the strengthening of the green environmental protection consciousness, it is an important research direction of integrated circuit that how to reduce power consumption at a high rate at the same time.The following three aspects are studied and designed:One is the research and design of CDR circuit for SerDes receiver. Firstly, the fundamental principle and structure of CDR are discussed. The design methods of the CDR based on PLL (Phase Locked Loop) are emphasized on, where various relevant building blocks, including PD (Phase Detector) FD (Frequency Detector), V/I (Voltage-to-Current) convertor, and VCO (Voltage-Controlled Oscillator) are introduced in detail. After studying PD and FD which may affect the work rate of CDR, a novel PFD (Phase/Frequency Detector) structure is presented which can greatly improve the speed of CDR. Lastly, The simulation of a behavioral model of PLL type CDR is carried out with MATLAB Simulink software, which provide the basis for the circuit parameters selection in the CDR transistor level design. The two is the research and design of the high speed and low power DEMUX circuit. Firstly, the power consumption of the different structures of DEMUX and the low-power design methods of the high-speed DEMUX are studied. Then, low power high-speed 5 division and 2 division circuit structures are also studied. The three is the integration of the SerDes receiver analog part. Chip integration should consider the problems of interface, the mutual influence of timing, interference and so on.Based on these theories and the design methods, a series of chips are designed in 0.18?m CMOS process.A 12.5 Gb/s half-rate Bang-Bang CDR circuit based on PLL and 1:2 DEMUX are designed and fabricated. The circuit incorporates a Bang-Bang PFD, a four-stage ring VCO, a V/I converter, a LF (Loop Filter), a 1:2 DEMUX and so on. The test results show that the tune range of VCO is about lGHz at 6.25 GHz centre frequency. When the data rate of the input pseudorandom is 12Gb/s, the recovered 6GHz clock has a root mean square (RMS) jitter of 1.9ps and a peak-to-peak jitter of 9.12ps. At the same time, the total chip can work well and the eye diagram of output data is clear. The core power consumption is only 150mW excluding the output buffers and the die size is 0.476×0.538 mm2.A 12.5Gb/s 1:10 DEMUX is fabricated. The whole circuit includes a high-speed 1:2 DEMUX, two serial low-speed 1:5 DEMUX, a 5 frequency divider and so on. The latch of the high-speed 1:2 DEMUX adopts the CML (Current Mode Logic) structure. The rest of the triggers all use E-TSPC (Extended True Single Phase Clock) structure. In the design of 5 frequency divider, the logic gate circuit is embedded in flip-flop to improve the work frequency. The test results show that when the data rate of the input pseudorandom is 12Gb/s and the clock frequency is 6GHz, this 1:10 DEMUX can work well and the eye diagram of output data is clear. The output swing is 324mV and the core power dissipation is 144. lmW excluding the output buffers. The die size is 0.64×0.57mm2.The analog circuits of 12.5Gb/s SerDes receiver are integrated. Because each module chip has been taped out and tested separately, the interface between modules need carefully design. The test results show that when the data rate of the input pseudorandom is 12Gb/s, this chip work well. The eye diagram of output data is clear and opens large. The core power consumption is 426.6mW excluding the output buffers and the die size is 0.758×0.645 mm2.A low power 10Gb/s 1:4 DEMUX with all-CMOS logic is fabricated. The tree-type structure is adopted in whole circuit including 1:2 demultiplexer cells,2 frequency divider cell, buffers for data and clock. The latch cells are implemented by using dynamic CMOS logic circuit. The transmission gate and inverter are utilized in buffers. The test results show that when the data rate of the input pseudorandom is 10Gb/s, this 1:4 DEMUX can work well. The output swing is 400mV and the chip power dissipation is 48.6mW. The die size is 0.475×0.475 mm2.A low-power multi-phase clock 20Gb/s 1:4 DEMUX is designed. The multi-phase clock architecture can avoid the high-speed 20Gb/s 1:2 DEMUX which is the part of most difficult design and maximum power consumption, and only keep the CMOS logic 10Gb/s 1:2 DEMUX among the tree-type structure. In the premise of ensuring the 1:4 DEMUX functionality and performance, the design can minimize the power consumption and the circuit design difficulty. The test results show that when the data rate of the input pseudorandom is 20Gb/s, this 1:4 DEMUX can work well. The output swing is 450mV and the chip power dissipation is 86mW. The die size is 0.475 ×0.475 mm2.