Research And Design Of Successive Approximation Analog - To - Digital Converter In UHF RFID Recognition

In recent years, the development of System-on-Chip (SoC) ultra-high frequency (UHF) band radio frequency identification (RFID) reader has reduced the cost and size of readers and enhanced the flexibility of the system. Focusing on low power ADCs in the reader, and combined with state of the art research of SAR ADC, this thesis utilizes a new structure applicable to high resolution, low power, and medium speed. The thesis completes the whole process of integrated circuit design, including the analysis of system structure, circuit design of each module, hardware implementation and test.In the system design stage, the main contributions and results are:1. Based on the analysis of SoC RFID system requirement, concrete design specifications of the ADC is calculated.2. According to the design specification, combined with state of the art research of SAR ADC, a novel structure using non-binary cap array and asynchronous timing is chosen.3. Non-ideal factors in this structure is analyzed to facilitate circuit design, including cap array mismatch, time constrains, and noise.In the circuit design stage, the main contributions and results are:4. Use small non-binary cap to reduce requirement of the process matching, which makes medium speed, high precision SAR ADC possible.5. In order to meet sample rate requirement, a pre-amplifier is added to the ADC system before signal comes into dynamic latch, which enhanced speed of the comparator and isolated kick-back noise.6. A variable delay module is designed to assure asynchronous timing could cover all process corner and different sample rate.In the test stage, the main contributions and results are:7. By comparing test and post simulation results, dominant error source, bonding wire inductance, is found.8. In order to stable reference voltage of ADC, a RC filter module is inserted. This chip is implemented using SMIC0.13um CMOS technology, the core voltage is1.2V (voltage of pre-amplifier is1.4V) and the core area including digital calibration module is0.082mm2. Test results demonstrate that peak ENOB is about9.5bit, and peak SFDR is about72dB. The whole chip consumes2.8mW power.