Research And Design Of A 14bit Successive Approximation Analog To Digital Converter

After 50 years of development since the advent of analogue-to-digital converters,the signal processing segment plays an important role in various systems and continues to be enhanced in today’s era of digitalisation in all walks of life.With the development of ADC technology,the outstanding performance of its Stepwise Approximation Analogto-Digital Converters(SAR ADCs)has attracted a lot of attention to / on the academic community.The aim at this thesis is to propose a new 14 bit SAR ADC which uses a hybrid capacitor-resistor structure and implements a high-performance circuit design through a comprehensive analysis of SAR ADCs.This thesis focuses on the design of a 14-bit,0.5MS/s SAR ADC with digital correction.this thesis provides an in-depth discussion of the current state of research on ADCs both at home and abroad,and details the various types of ADCs,as well as the important parameters used to evaluate system.The toplevel circuit of the system is simulated in this thesis based on a 0.13μm 1P6 M CMOS process of a mixed digital-to-analogue design.The design uses a circuit design that incorporates a pre-amplifier before the latching comparator,which consists of an internal bias start circuit,op-amp circuit,Latch comparator and RS flip-flop output stage,to achieve the circuit function of a high-speed,high-precision comparator.By using the offset suppression technique,the voltage imbalance of the comparator can be effectively suppressed,thus improving the conversion accuracy and greatly reducing the power consumption;in addition,this thesis also adopts a gate voltage bootstrap circuit structure,which can effectively to reduce the sampling error.A hybrid capacitor-resistor(C-R)DAC structure is used for the construction of the DAC,which is an important module in this circuit.The performance of the high-level circuit is improved by using a proportional reduction in charge to the DAC,thereby improving the accuracy and reliability of the circuit.For low-level circuits,we can use a single resistor to divide the voltage,thus reducing the layout area of the circuit.Through the design of the Cadence platform,we use the Matlab software to supply dual power supplies to the ADC,with one supply outputting 1.2V and the other 3.3V,as well as an10 MHz clock frequency,to achieve effective control of the ADC.After simulation,we find that the ENOB is 11.78 bits when the input sine voltage reaches 1.65 V and the frequency is 249 k Hz,after calibration the ENOB is 13.1 bits and the dynamic characteristics are excellent.The power consumption is 1.5m W for the analogue part and 0.156 m W for the digital part.