Research And Design Of High-precision Hundreds MSPS Pipelined SAR Analog-to-digital Converter

The booming trend of the integrated circuit industry has promoted social science and technology to continuously move forward.The integrated circuit can be seen everywhere in emerging areas such as the Internet of Things,artificial intelligence,and 5G communication,and the natural signal that we feel around us will be converted into a electrical signal.ADC is a solid bridge for these applications.The computer can achieve various functions by processing the conversion digital signal.With the rapid development of digital signal processing capabilities,the comprehensive consideration of the speed,accuracy and energy consumption of the conversion terminal is put forward.Become the core of the ADC design scheme.As a comprehensive architecture,the pipelined SAR ADC is approached one by one,combined with the advantages of the pipelined ADC and the SAR ADC.Realize the high-level high-speed and low-power in parallel of flowing water and low-power features that approach one by one.In recent years,it has gradually become a topic of extensive research in academic circles.Pipelined Sar ADC has achieved high precision of research on the premise of maintaining high speed and low power consumption.The Pipelined SAR ADC designed in this article adopts the first level 6,the second level 5-digit resolution segmentation solution.Each level adopts non-binary internal redundancy to increase the speed of DAC,1 redundant at the same time,increase the second level of quantitative fault tolerance.The second-level reference voltage range has been attenuated by 8 times,which reduces the gain requirements of the residual amplifier.The residual amplifier adopts a switch capacitor,which has excellent stability under different PVT conditions.The internal op amp uses a two-stage structure.The first level is a high gain for the folding co-source grid.The second level is the Class-AB output level.High bandwidth,increase the speed of the establishment of the op amp.In the traditional Pipelined SAR ADC architecture,through the addition of the switching load capacitor switch circuit,the load capacitance with a second-level noise signal is controlled through a certain time-sequential time-order feedback capacitor to achieve a first-order error feedback noise plastic surgery effect.At the same time,at the same time ADC dynamic performance is improved by 8 times over-sampling and digital filtering technology filtering except for noise.The thesis first performs behavioral modeling through MATLAB to verify the feasibility of the "6+5" segment structure,and comprehensively considers the impact of various irrational factors on dynamic performance.Then use the Cadence simulation platform to build circuit based on the 40 nm CMOS process.With the 1.8V power supply voltage and 200 MHz sampling rate,8 times over sampling and digital filtering in addition to except for noise.At the same time the first-order error feedback noise plastic surgery realizes the effectiveness of 12.07 Bits,reaching the SFDR 90.81 d B and SNDR of74.43 d B,with a total energy consumption of 7.32 m W.