Design Of A Pipelined-SAR ADC With A Novel Low-power Sub-ADC

With the continuous development of computer technology and digital signal processing technology,the demand for digital signals is getting higher and higher,so the role of Analog-to-Digital Converters(ADCs)becomes more important.The PipelinedSAR ADC has many advantages over other types,especially in terms of speed,accuracy,area,and power consumption.Therefore,it has become a hot research object in the field of analog-to-digital conversion in recent years.This article designs a 14-bit Pipelined-SAR ADC based on the 22 nm FDSOI CMOS process.The overall circuit includes: SAR ADC,inter-stage amplifier,and digital logic module.It uses asynchronous sequential logic and four-stage pipeline structure.The sub-ADC uses SAR ADC instead of flash ADC.SAR ADC mainly includes CDAC,comparator,and some digital modules.Each stage of the pipeline uses a multi-comparator structure and a capacitor-splitting digital-to-analog converter(CDAC)to achieve a tradeoff between speed and performance.A binary-weighted capacitor array using a differential structure,using an upper plate sampling technology,and using a split capacitor to make the common mode level of the CDAC always a constant value,so that the comparator input voltage common mode level can be maintained stable.Because the SAR ADC uses CDAC,there is no need to use additional sample-and-hold circuits.The sample-and-hold function can be completed by CDAC.At the same time,the high-speed and high-precision bootstrap switch circuit is used to improve the accuracy of the sample switch and greatly reduce the influence of switching nonlinearity on the accuracy of the ADC.The ADC uses a Strong ARM-Latch comparator with a pre-amplification stage,which is fast and has low noise and offset.The inter-stage amplifier between adjacent two stages uses a dynamic amplifier structure with low power consumption and noise.By adding one redundant bit to each of the last three stages of the pipeline,the residual signal over-range problem caused by comparator offset and amplifier offset is solved,thereby reducing the impact on ADC performance.A digital calibration algorithm based on comparator metastable detection technology is proposed.This calibration algorithm,with PN code generation circuit and metastable detection circuit,can calibrate the gain of the inter-stage amplifier,the comparator offset and the capacitor mismatch to improve the ADC performance.The previous simulation results of the overall circuit of the Pipelined-SAR ADC show that when the power supply voltage is 0.8 V,the sampling rate is 800 MHz and input sine signal frequency is 82.8125 MHz,the effective number of bits(ENOB)is 12.28 bit and the total power consumption of the core circuit is about 28.92 mW.