Research On Column-Level SAR/SS ADC For CMOS Image Sensor

With the development of the times,people's pursuit of high-quality life promotes the progress of science and technology.CMOS image sensor is an important component of modern electronic equipment.Its performance has a direct impact on the imaging effect.At present,its main expansion direction is high frame rate,large dynamic range and low power consumption.The requirements for CMOS image sensors have also directly promoted the development of column-level analog-to-digital converters(ADC,analog to digital converters),which are their core components.This paper compares different types of commonly used column-level ADCs and proposes a structure that combines successive approximation analog to digital converters(SAR ADC)and single-slope analog to digital converters(SS ADC).This structure complements the advantages of the two.It not only has the advantages of conversion speed of SAR ADC,but also does not occupy too much area due to the combination of SS ADC.SAR/SS ADC includes comparators,ramp generators,capacitor arrays,counters and other modules.The SAR ADC part and the SS ADC part perform high and low 6 bit conversions to complete 12 bit analog-to-digital data conversion.Among them,the capacitor array adopts a 2+4 segmentation method,and the bridging capacitor can not only realize the function of SAR but also save the area.The comparator is a differential input mode,and uses the sampling capacitor for offset calibration.The two signals are input to the reset signal and the sampling signal respectively.The sampling capacitor stores the offset voltage of the input signal and the comparator respectively,so that the offset voltage can be approximately eliminated during comparison.At the same time,the differential input method can perform correlated double sampling processing on the signal to achieve a more ideal effect.After the high-bit conversion,the high-bit data is not stored in the sampling capacitor,but is stored through the capacitor array required for the high-bit conversion.This determined value is then compared with the ramp signal to complete the final SS ADC low-bit conversion.The design of this paper is based on 0.18?m CMOS process,and the design verification is completed in the auxiliary software environment.The input analog/digital voltage signal is 3.3V/1.8V,the quantization range is 2V,and in the sampling frequency of 20 MSps,the effective number of digits reaches 10.4 bit.