| In the era of big data,in order to transmit signals at high speed,data centers maintain the demand for time-interleaved Analog-to-Digital Converters(ADCs)with 5 bits enob and a sampling rate of 56GS/s.The ADC is implemented by interleaving dozens of 6-8bit high speed sub-ADC.Considering the mismatch and power consumption of multi-channel ADC,single channel ADC pursues high sampling rate,high effective precision and low power consumption.Pipeline SAR ADCs are widely used in medium-precision high-speed ADCs because of their structural characteristics.Applying for data centers,an 8bit 1.2GS/s Pipeline SAR ADC in Voltage Domain is designed,which uses switches to transfer the residue voltage.The Pipeline SAR ADC designed is a two-stage structure.Two stage SAR ADCs realizes 4bit and 5bit respectively,1bit interstage redundancy is set.In the first-stage SAR ADC,the bootstrap circuit with a module reducing capacitive coupling is used,which ensures the linearity of sampling switch.With analysis of the kickback noise and memory effect in high-speed dynamic comparator,the circuit is improved by adding a PMOS tail current mosfet and cross-coupled dummy mosfets,raising the source voltage of differential input pair to VDD during reset phase,speeding up the reset of the comparator.The multiplier circuit is used between the stages to control the switch for improving speed,compared with bootstrap in the case of sampling small signals,and the corresponding digital control logic is designed.In the second-stage SAR ADC,due to the low amplitude of the sampled signal,a high-speed low-noise dynamic comparator is proposed,and a module for metastability detection and correction is designed.Simulation results show that comparator input-referred noise is significantly reduced and the metastability correction is performed effectively under the condition of introducing a small amount of delay,ensuring the accuracy and linearity of the second-stage SAR ADC.In order to reduce the influence of comparator offset,a charge-sharing foreground offset calibration scheme is used to reduce the absolute offset of the comparator and avoid wasting extra calibration time.Based on TSMC 28 nm CMOS process,the circuit and layout are designed.The postsimulation results show that under 1V supply voltage,when the sampling rate is 1.2GS/s,under TT corner the ENOB at Nyquist frequency input can reach 7.61 bit,the SFDR is 56.9d Bc,the power consumption is 3.26 m W.The simulation results meet the design requirements. |
