Design Of High-speed Low-power Comparator In 16Gb/s SerDes DFE

In recent years,with the advent of 5G technology and the Internet of things era,the scale of data has begun to expand rapidly,and people's demand for high-speed communication systems is increasing.In order to meet the requirements of high-speed data transmission,serializer / deserializer(Ser Des)technology has developed at incredible speed,and highspeed and high-performance Ser Des has become a research hotspot in the field of data transmission.Equalization technology is the key to high-speed data transmission.As a nonlinear equalizer,Decision feedback equalizer(DFE)is widely used in Ser Des receiver owing to its robustness without noise amplification.One vital component of a DEF is the comparator,of which the speed,power consumption and offset would strongly influence the performance of a DFE.This paper is based on a practical project in an enterprise.A highspeed and low-power comparator for decision feedback equalizer in 16Gb/s Ser Des system is designed.The demand for ultra-low power,low area and high-speed analog-to-digital converter circuits has continuously promoted the development of comparators.In the field of high speed and low power consumption,comparators are required to maximize speed and energy efficiency.In all kinds of comparator structures,double-tail dynamic comparator is widely used in various high-speed data transmission systems because of its advantages of high speed and low power consumption.In this paper,a high-speed,low-power and low-offset dynamic comparator is proposed based on the optimization of double-tail dynamic comparator.Compared with the traditional double-tail dynamic comparator,the dynamic comparator proposed in this paper can effectively reduce the latch response time in the regeneration stage,thereby reducing the overall delay of the comparator.At the same time,the input offset voltage of the comparator is significantly reduced by using offset elimination technology.The dynamic comparator includes latches,preamplifiers and offset cancellation circuits.In terms of designs of each part,firstly the dynamic latch is involved with benefits of high speed and low power consumption,and a large kick back noise is introduced at the input end.The dynamic latch is then connected with a preamplifier via the gate of the NMOS tube to suppress the kick back noise effectively.Secondly,according to the application requirements of the DEF,the reference voltage differential pair is added to the preamplifier,and the threshold voltage of the comparator can be adjusted according to the reference voltage differential to meet various threshold voltage requirements.In order to improve the speed of the dynamic comparator,the preamplifier structure is improved,and a positive feedback structure is introduced to make the preamplifier output larger in the decision phase of the comparator,so as to speed up the regeneration of the dynamic latch.In order to reduce the offset voltage of the comparator,the offset voltage elimination circuit is designed.Through in-depth theoretical analysis,the offset voltage of the dynamic comparator mainly comes from the preamplifier,which can eliminate the offset voltage by adding series capacitor and transmission gate control circuit to the differential input of the preamplifier.There is no quiescent current in this circuit structure,so that the power consumption of the dynamic comparator will not increase significantly.In this paper,SMIC 28 nm CMOS technology is used to verify the dynamic comparator's pre-simulation,layout design and post-simulation.The post-simulation results of the dynamic comparator show that when the supply voltage is 1 V and the clock signal frequency is 8 GHz,the transmission delay of the comparator is 37.7 PS,the establishment time is 11.8 PS,the power consumption is 2 m W,the offset voltage is 1.54 m V,and the duty cycle of the comparator is 54.1%.Compared with the existing comparator structure,this design reduces the transmission delay and input offset voltage of the comparator,while basically does not increase the power consumption and circuit structure complexity.