The Design Of High-speed Low-power Comparator

Analog-to-digital converters (ADCs) are important building blocks in many electronic applications.With the rapid development of video and communication technology,high-speed,medium-resolution ADCs requirements are increasing.Various architectures have been used to deliver these high-speed,medium-resolution ADCs.Of these,pipeline architecture has proven to be the most efficient for applications.The comparator is a crucial part of ADC.Its speed and power have great impact on the characteristic of the whole ADC.Being one of various architectures,preamplifier-latch is widely used as high-speed comparator due to its high-speed,low-power and small offset voltage. Based on preamplifier-latch comparator, adopted TSMC 0.13μm CMOS process,a high-speed,low-power comparator applied for pipelined-ADC is proposed in this paper.Besides,the layout was designed and taped out. This comparator consists of three blocks:latch,pre-amplifier and switched capacitor circuit.With fast response and low power consumption,latch has large offset voltage and kick back noise.Pre-amplifier can increase the speed of the comparator.Besides,it can also reduce offset voltage and inhibit the kick back noise.In order to reduce the offset voltage further,auto-zero technology was used by adding switched capacitor circuit,then the comparator can compare the differential signal.The post simulation result showed the power consumption of the comparator was 0.505mW at 500MHz and 0.336mW at 125MHz.Experimental results showed that the power consumption was 0.36mW at 500MHz and the offset voltage achieved 5mV.The comparator satisfies pipelined-ADC performance requirements when the input voltage rang is 450mV~950mV.