Design Of 16-bit Low-power SAR ADC

In biomedical systems and wearable devices,the detected human body state parameters need to be converted into digital signals through an analog-to-digital converter(ADC)for processing.As the key module of the system,ADC usually needs to achieve high accuracy and reduce power consumption as much as possible.Among many types of analog-to-digital converters,successive approximation register(SAR)analog-to-digital converters can meet the requirements of equipment for accuracy and energy efficiency due to its structural advantages.Therefore,the design of a low-power and high-precision SAR ADC has research significance and practical value.The research status of low-power high-precision SAR ADC at home and abroad,and the main low-power high-precision technology are summarized in this thesis.On this basis,system-level,circuit level and layout design are carried out.The advantages and disadvantages of the digital-to-analog converter(DAC)suitable for high precision design are analyzed and compared.The effects of device mismatch and parasitic capacitance on the gain and linearity of DAC are deduced and verified by simulation.An integer non-binary capacitor array is proposed,which can reduce the error of capacitor mismatch and improve the speed of CDAC by redundancy technology.According to capacitor mismatch problem,a kind of digital calibration scheme based on pseudo random code injection is proposed,the actual weight value of capacitance is iterated through the least mean square(LMS)algorithm.While ensuring the sampling rate,excessive hardware and power consumption are avoided.In addition,the offset voltage of the cascade comparator is calibrated based on output offset storage(OOS)technology and current allocation is optimized to meet the design requirements of low power consumption.Based on the SMIC 180nm 1.8V standard CMOS process,the circuit and layout are designed.The ADC core area is about 0.455mm~2,and the whole area is 1mm~2.The post-simulation verification is carried out at 1.8V power supply voltage and 500k S/s sampling rate.When the input signal is near Nyquist frequency,the signal-to-noise distortion ratio(SNDR)is89.4d B,the effective bit(ENOB)is 14.56bit,the spurious dynamic ratio(SFDR)is 98.2d Bc,the power consumption is 0.83m W(Not including calibration circuit power consumption),and the figure of merit(FOM_S)is 171d B,meeting the design index requirements basically.