Research And Design Of Multichannel Clock Interleaved SAR ADC

Time-interleaved ADC of high speed and medium resolution has wide range of application such as hard-disk read channel, digital oscilloscopes, optical communications and serial links transceivers. Moreover, with the trend of reconfigurable wireless transceiver and placing the ADC as near the antenna as possible, time-interleaved ADC has been the hotspot in the area of integrated circuits.There are two key parts in the focus research of time-interleaved ADC, the time-skew calibration algorithm between channels and SAR ADC of the single channel, which were both analyzed and designed in this dissertation. Eliminating the degradation of SNR caused by the time-skew between channels is the crucial technique in time-interleaved ADC design. To calibrate the time-skews, two current calibration methods have been combined to take advantage of their merits and a minimum zero-crossing calibration algorithm is proposed. When it turns to the part of SAR ADC, the successive approximation register structure which is best suited to high speed, low power and medium resolution applications was adopted. The three main blocks including DAC, comparator and SAR logic were designed, respectively. The performance deterioration of DNL&INL caused by capacitor mismatch and parasitic capacitors of DAC was deduced in detail. What’s more, the offset of comparator introduced by the mismatch was also discussed and a calibration circuit which is composed of a comparator, offset compensation current, logic units and a charge pump has been adopted in the design.Random skews are introduced for each channel and the calibration algorithm is simulated. The sampling rate of whole ADC is1GS/s and random time skews ranging from-127ps to127ps are introduced with lps calibration step. With inputs of different frequencies, SNRs of these frequency points after calibration achieve about49dB which corresponds to a7.8bit performance gain.The SAR ADC of single channel has been manufactured in SMIC0.13um1P8M CMOS technology. The simulation results revealed that the SNDR and SFDR is50.3dB and63.3dB with input signal of low frequency,48.1dB and58dB with input of high frequency. The power consumption of SAR ADC is5.86mW. The measurement results verified the feasibility of the SAR ADC chip.